Datasheet

2−11
2.15.2.2Read Phase 2
Step 7 0
I
2
C Start (master) S
Step 8 7 6 5 4 3 2 1 0
I
2
C General address (master) 1 0 1 1 1 0 X 1
Step 9 9
I
2
C Acknowledge (slave) A
Step 10 7 6 5 4 3 2 1 0
I
2
C Read data (slave) Data Data Data Data Data Data Data Data
Step 11
†
9
I
2
C Not acknowledge (master) A
Step 12 0
I
2
C Stop (master) P
†
Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
2.15.2.3I
2
C Timing Requirements
The TVP5150A decoder requires delays in the I
2
C accesses to accommodate its internal processor’s timing. In
accordance with I
2
C specifications, the TVP5150A decoder holds the I
2
C clock line (SCL) low to indicate the wait
period to the I
2
C master. If the I
2
C master is not designed to check for the I
2
C clock line held-low condition, then the
maximum delays must always be inserted where required. These delays are of variable length; maximum delays are
indicated in the following diagram:
Normal register writing address 00h−8Fh (addresses 90h−FFh do not require delays)
Start
Slave address
(B8h)
Ack Subaddress Ack
Data
(XXh)
Ack Wait 64 µs Stop
2.16 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL.
This may be input to the TVP5150A decoder on terminal 5 (XTAL1), or a crystal of 14.31818-MHz fundamental
resonant frequency may be connected across terminals 5 and 6 (XTAL2). Figure 2−5 shows the reference clock
configurations. For the example crystal circuit shown (a parallel-resonant crystal with 14.31818-MHz fundamental
frequency), the external capacitors must have the following relationship:
C
L1
= C
L2
= 2C
L
− C
STRAY
,
where C
STRAY
is the terminal capacitance with respect to ground. Figure 2−5 shows the reference clock
configurations.
TVP5150A
5
XTAL1
14.31818-MHz
Crystal
6
XTAL2
TVP5150A
5
XTAL1
6
XTAL2
C
L1
C
L2
14.31818-MHz
TTL Clock
Figure 2−5. Reference Clock Configurations