Datasheet

2−9
2.15 I
2
C Host Interface
The I
2
C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which
carry information between the devices connected to the bus. A third signal (I2CSEL) is used for slave address
selection. Although the I
2
C system can be multimastered, the TVP5150A decoder functions as a slave device only.
Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is free, both
lines are high. The slave address select terminal (I2CSEL) enables the use of two TVP5150A decoders tied to the
same I
2
C bus. At power up, the status of the I2CSEL is polled. Depending on the write and read addresses to be used
for the TVP5150A decoder, it can either be pulled low or high through a resistor. This terminal is multiplexed with
YOUT7 and hence must not be tied directly to ground or V
DD
. Table 2−6 summarizes the terminal functions of the
I
2
C-mode host interface.
Table 2−5. Write Address Selection
I2CSEL WRITE ADDRESS
0 B8h
1 BAh
Table 2−6. I
2
C Terminal Description
SIGNAL TYPE DESCRIPTION
I2CSEL (YOUT7) I Slave address selection
SCL I/O (open drain) Input/output clock line
SDA I/O (open drain) Input/output data line
Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is dependent on
the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL except
for start and stop conditions. The high or low state of the data line can only change with the clock signal on the SCL
line being low. A high-to-low transition on the SDA line while the SCL is high indicates an I
2
C start condition. A
low-to-high transition on the SDA line while the SCL is high indicates an I
2
C stop condition.
Every byte placed on the SDA must be 8 bits long. The number of bytes which can be transferred is unrestricted. Each
byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the I
2
C master.
2.15.1 I
2
C Write Operation
Data transfers occur utilizing the following illustrated formats.
An I
2
C master initiates a write operation to the TVP5150A decoder by generating a start condition (S) followed by
the TVP5150A I
2
C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the TVP5150A decoder, the master presents the subaddress of the register, or the
first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP5150A decoder
acknowledges each byte after completion of each transfer. The I
2
C master terminates the write operation by
generating a stop condition (P).
Step 1 0
I
2
C Start (master) S
Step 2 7 6 5 4 3 2 1 0
I
2
C General address (master) 1 0 1 1 1 0 X 0
Step 3 9
I
2
C Acknowledge (slave) A
Step 4 7 6 5 4 3 2 1 0
I
2
C Write register address (master) addr addr addr addr addr addr addr addr