Datasheet

2−8
HSYNC
AVID Start
AVID Stop
VBLK Stop
VBLK Start
VSYNC
AVID Cropped
Area
Active Video Area
Figure 2−4. AVID Application
2.14 Embedded Syncs
Standards with embedded syncs insert SAV and EAV codes into the datastream at the beginning and end of horizontal
blanking. These codes contain the V and F bits which also define vertical timing. F and V change on EAV. Table 2−4
gives the format of the SAV and EAV codes.
H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and field
counter varies depending on the standard. Please refer to ITU-R BT.656 for more information on embedded syncs.
The P bits are protection bits:
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
Table 2−4. EAV and SAV Sequence
8-BIT DATA
D7 (MSB) D6 D5 D4 D3 D2 D1 D0
Preamble 1 1 1 1 1 1 1 1
Preamble 0 0 0 0 0 0 0 0
Preamble 0 0 0 0 0 0 0 0
Status word 1 F V H P3 P2 P1 P0