Datasheet

2−5
IDID1: Bit 0/1 = Transaction video line number [9:8]
Bit 2 = Match 2 flag
Bit 3 = Match 1 flag
Bit 4 = 1 if an error was detected in the EDC block. 0 if not.
CS: Sum of D0−D7 of DID through last data byte.
Fill byte: Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte. For teletext modes, byte 8 is the sync pattern
byte. Byte 9 is 1. Data (the first data byte).
2.10 Raw Video Data Output
The TVP5150A decoder can output raw A/D video data at 2x sampling rate for external VBI slicing. This is transmitted
as an ancillary data block during the active horizontal portion of the line and during vertical blanking.
2.11 Output Formatter
The YCbCr digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.656 parallel interface standard.
Table 2−3. Summary of Line Frequencies, Data Rates, and Pixel Counts
STANDARDS
HORIZONTAL
LINE RATE (kHz)
PIXELS PER
LINE
ACTIVE PIXELS
PER LINE
SCLK FREQUENCY
(MHz)
NTSC (M, 4.43), ITU-R BT.601 15.73426 858 720 27.00
PAL (B, D, G, H, I), ITU-R BT.601 15.625 864 720 27.00
PAL (M), ITU-R BT.601 15.73426 858 720 27.00
PAL (N), ITU-R BT.601 15.625 864 720 27.00
SECAM, ITU-R BT.601 15.625 864 720 27.00
2.12 Synchronization Signals
External (discrete) syncs are provided via the following signals:
• VSYNC (vertical sync)
• FID/VLK (field indicator or vertical lock indicator)
• GPCL/VBLK (general-purpose I/O or vertical blanking indicator)
• PALI/HLK (PAL switch indicator or horizontal lock indicator)
• HSYNC (horizontal sync)
• AVID (active video indicator)
VSYNC, FID, PALI, and VBLK are software-set and programmable to the SCLK pixel count. This allows any possible
alignment to the internal pixel count and line count. The default settings for a 525-/625-line video output are given
as an example below.