!" #$ Data Manual September 2003 HPA Digital Audio Video SLES087
Contents Section 1 2 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Related Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.
2.20.2 2.20.3 2.20.4 2.20.5 2.20.6 2.20.7 2.20.8 2.20.9 2.20.10 2.20.11 2.20.12 2.20.13 2.20.14 2.20.15 2.20.16 2.20.17 2.20.18 2.20.19 2.20.20 2.20.21 2.20.22 2.20.23 2.20.24 2.20.25 2.20.26 2.20.27 2.20.28 2.20.29 2.20.30 2.20.31 2.20.32 2.20.33 2.20.34 2.20.35 2.20.36 2.20.37 2.20.38 2.20.39 2.20.40 2.20.41 2.20.42 2.20.43 2.20.44 2.20.45 iv Analog Channel Controls Register . . . . . . . . . . . . . . . . . . . . Operation Mode Controls Register . . . . . . . . . . . . . . . . . . . .
3 4 5 6 2.20.46 Status Register #4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.20.47 Status Register #5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.20.48 Closed Caption Data Registers . . . . . . . . . . . . . . . . . . . . . . . 2.20.49 WSS Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.20.50 VPS Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.20.51 VITC Data Registers . . . . . . . .
List of Illustrations Figure 1−1 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 3−1 3−2 5−1 Title Page Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Composite Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bit 4:2:2, Timing With 2x Pixel Clock (SCLK) Reference . . . . . . . . . . . . Horizontal Synchronization Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVID Application . . . . . . . . . . .
1 Introduction The TVP5150A device is an ultralow power NTSC/PAL/SECAM video decoder. Available in a space saving 32-pin TQFP package, the TVP5150A decoder converts NTSC, PAL, and SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also available. The optimized architecture of the TVP5150A decoder allows for ultralow-power consumption.
• Fully differential CMOS analog preprocessing channels with clamping and automatic gain control (AGC) for best signal-to-noise (S/N) performance • Ultralow power consumption: 115 mW typical • 32-pin TQFP package • Power-down mode: <1 mW • Brightness, contrast, saturation, hue, and sharpness control through I2C • Complementary 4-line (3-H delay) adaptive comb filters for both cross-luminance and cross-chrominance noise reduction • Patented architecture for locking to weak, noisy, or unstable si
1.4 Ordering Information PACKAGED DEVICES TA PACKAGE OPTION 32TQFP-PBS 0°C to 70°C TVP5150APBS Tray 0°C to 70°C TVP5150APBSR Tape and reel 1.
1.6 Terminal Assignments CH_AVDD CH_AGND REFM REFP PDN INTREQ/GPCL/VBLK AVID HSYNC TQFP PACKAGE (TOP VIEW) 1 32 31 30 29 28 27 26 25 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 10 11 12 13 14 15 16 VSYNC/PALI FID/GLCO SDA SCL DVDD DGND YOUT0 YOUT1 PCLK/SCLK IO_DVDD YOUT7/I2CSEL YOUT6 YOUT5 YOUT4 YOUT3 YOUT2 AIP1A AIP1B PLL_AGND PLL_AVDD XTAL1/OSC XTAL2 AGND RESETB 1.7 Terminal Functions Table 1−1.
Table 1−1. Terminal Functions (Continued) TERMINAL NAME NUMBER I/O DESCRIPTION Digital Section AVID 26 O Active video indicator. This signal is high during the horizontal active time of the video output. AVID toggling during vertical blanking intervals is controlled by bit 2 of the active video cropping start pixel LSB register at address 12h (see Section 2.20.18). DGND 19 I Digital ground DVDD 20 I Digital supply. Connect to 1.
2 Functional Description 2.1 Analog Front End The TVP5150A decoder has an analog input channel that accepts two video inputs, which are ac-coupled. The decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is needed for most input signals with a peak-to-peak variation of 1.5 V. The maximum parallel termination before the input to the device is 75 Ω.
Gain Factor Peak Detector Bandpass X Peaking Composite Delay Line Delay + Delay − Y Y Quadrature Modulation Contrast Brightness Saturation Adjust SECAM Luma Cr Notch Filter Cb Composite SECAM Color Demodulation Cb Composite Quadrature Modulation Cr Cr Notch Filter Color LPF ↓ 2 Burst Accumulator (Cb) Cb 4-Line Adaptive Comb Filter Color LPF ↓ 2 LP Filter LP Filter Delay Delay Burst Accumulator (Cr) Figure 2−1. Composite Processing Block Diagram 2.
2.7 Timing Processor The timing processor is a combination of hardware and software running in the internal microprocessor that serves to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the analog front end, vertical sync detection, and Macrovisiont detection. 2.8 VBI Data Processor The TVP5150A VBI data processor (VDP) slices various data services like teletext (WST, NABTS), closed caption (CC), wide screen signaling (WSS), etc.
At powerup the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents with the lookup table (see Section 2.20.58). This is done through port address C3h. Each read from or write to this address will auto increment an internal counter to the next RAM location. To access the VDP-CRAM, the line mode registers (D0h−FCh) must be programmed with FFh to avoid a conflict with the internal microprocessor and the VDP in both writing and reading. Full field mode must also be disabled.
IDID1: Bit 0/1 = Transaction video line number [9:8] Bit 2 = Match 2 flag Bit 3 = Match 1 flag Bit 4 = 1 if an error was detected in the EDC block. 0 if not. CS: Sum of D0−D7 of DID through last data byte. Fill byte: Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte. For teletext modes, byte 8 is the sync pattern byte. Byte 9 is 1. Data (the first data byte). 2.10 Raw Video Data Output The TVP5150A decoder can output raw A/D video data at 2x sampling rate for external VBI slicing.
525-Line 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 Composite Video VSYNC FID GPCL/VBLK ↔ VBLK Start 262 263 ↔ VBLK Stop 264 265 266 267 268 269 270 271 272 273 282 283 284 Composite Video VSYNC FID GPCL/VBLK ↔ VBLK Start ↔ VBLK Stop 625-Line 310 311 312 313 314 315 316 317 318 319 320 333 334 335 336 Composite Video VSYNC FID GPCL/VBLK ↔ VBLK Start 622 623 624 ↔ VBLK Stop 625 1 2 3 4 5 6 7 20 21 22 23 Composite Video VSYNC FID GPCL/VBLK ↔ VBLK Start N
ITU-R BT.656 timing. NTSC 601 1436 1437 1438 1439 1440 1441 … 1455 1456 … 1583 1584 … 1711 1712 1713 1714 1715 PAL 601 1436 1437 1438 1439 1440 1441 … 1459 1460 … 1587 1588 … 1723 1724 1725 1726 1727 ITU 656 Cb Datastream 359 Y 718 Cr 359 … … Y 719 FF 00 10 80 10 80 … 10 FF 00 00 XX 0 1 2 3 0 1 2 3 Cb 0 Y 0 Cr 0 Y 1 HSYNC ↔ HSYNC Start AVID ↔ AVID Stop ↔ AVID Start NOTE: AVID rising edge occurs 4 SCLK cycles early when in the ITU-R BT.656 output mode.
VBLK Stop Active Video Area VBLK Start AVID Cropped Area AVID Start VSYNC AVID Stop HSYNC Figure 2−4. AVID Application 2.14 Embedded Syncs Standards with embedded syncs insert SAV and EAV codes into the datastream at the beginning and end of horizontal blanking. These codes contain the V and F bits which also define vertical timing. F and V change on EAV. Table 2−4 gives the format of the SAV and EAV codes. H equals 1 always indicates EAV. H equals 0 always indicates SAV.
2.15 I2C Host Interface The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CSEL) is used for slave address selection. Although the I2C system can be multimastered, the TVP5150A decoder functions as a slave device only. Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is free, both lines are high.
Step 5 I2C Acknowledge (slave) Step 6 I2C Write data (master) 9 A 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data Step 7† I2C Acknowledge (slave) A Step 8 I2C Stop (master) P 9 0 † Repeat steps 6 and 7 until all data have been written. 2.15.2 I2C Read Operation The read operation consists of two phases. The first phase is the address phase.
2.15.2.2 Read Phase 2 Step 7 I2C Start (master) 0 S Step 8 I2C General address (master) Step 9 I2C Acknowledge (slave) 7 6 5 4 3 2 1 0 1 0 1 1 1 0 X 1 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data 9 A Step 10 I2C Read data (slave) Step 11† I2C Not acknowledge (master) 9 A Step 12 0 I2C Stop (master) P † Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received. 2.15.2.
2.17 Genlock Control and RTC A Genlock control (GLCO) function is provided to support a standard video encoder to synchronize its internal color oscillator for properly reproduced color with unstable timebase sources like VCRs. The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the subcarrier phase reset bit are transmitted via terminal 23 (GLCO). The frequency control word is a 23-bit binary number.
2.17.2 RTC Mode Figure 2−7 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is 4 times slower than the GLCO clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control bit is 2 clock cycles long. The active low reset bit occurs 6 CLKs after the transmission of the last bit of PLL frequency control. RTC 128 CLK 16 CLK M S B L S B 21 0 44 CLK 22-Bit Fsc Frequency Control 2 CLK 1 CLK PAL Switch 2 CLK Start Bit 3 CLK 1 CLK Reset Bit Figure 2−7.
Table 2−9.
Table 2−9.
2.20 Register Definitions 2.20.1 Video Input Source Selection #1 Register Address 00h Default 00h 7 6 5 4 Reserved 3 2 1 0 Black output Reserved Channel 1 source selection S-video selection Channel 1 source selection: 0 = AIP1A selected (default) 1 = AIP1B selected Table 2−10.
2.20.3 Operation Mode Controls Register Address 02h Default 00h 7 6 Reserved Color burst reference enable 5 4 TV/VCR mode 3 2 1 0 White peak disable Color subcarrier PLL frozen Luma peak disable Power down mode Color burst reference enable 0 = Color burst reference for AGC disabled (default) 1 = Color burst reference for AGC enabled TV/VCR mode 00 = Automatic mode determined by the internal detection circuit.
2.20.
0F(Bit 2) VSYNC/PALI 0F(Bit 4) LOCK24B VSYNC PALI HLK 0 HVLK 1 HVLK 1 VLK 0 0 M U X HLK/HVLK 1 M U X VLK/HVLK 1 FID 0 0 M U X PALI/HLK/HVLK 1 M U X FID/VLK/HVLK 0 GLCO 1 M U X VSYNC/PALI/HLK/HVLK M U X FID/GLCO/VLK/HVLK Pin 24 Pin 23 0F(BIT 6) LOCK23 0F(BIT 3) FID/GLCO 03(Bit 4) HVLK VBLK 1 GPCL 0 M U X VBLK/GPCL INTREQ 1 0 M U X INTREQ/GPCL//VBLK Pin 27 SCLK 03(BIT 7) VBKO PCLK 0 1 0F(BIT 1) INTREQ/GPCL/VBLK M U X PCLK/SCLK Pin 9 0F(BIT 0) SCLK/PCLK Figu
2.20.5 Autoswitch Mask Register Address 04h Default FCh 7 6 Reserved 5 4 3 2 SEC_OFF N443_OFF PALN_OFF PALM_OFF 1 0 Reserved N443_OFF: 0 = NTSC443 is unmasked from the autoswitch process. Autoswitch does switch to NTSC443. 1 = NTSC443 is masked from the autoswitch process. Autoswitch does not switch to NTSC443. (default) PALN_OFF: 0 = PAL-N is unmasked from the autoswitch process. Autoswitch does switch to PAL-N. 1 = PAL-N is masked from the autoswitch process.
2.20.8 Luminance Processing Control #1 Register Address 07h Default 60h 7 2x luma output enable 6 5 4 Pedestal not present Disable raw header Luma bypass enabled during vertical blanking 3 2 1 0 Luminance signal delay with respect to chrominance signal 2x luma output enable: 0 = Output depends on bit 4, luminance bypass enabled during vertical blanking (default). 1 = Outputs 2x luma samples during the entire frame. This bit takes precedence over bit 4. Pedestal not present: 0 = 7.
2.20.9 Luminance Processing Control #2 Register Address 08h Default 00h 7 6 Reserved Luminance filter select 5 4 3 Reserved 2 1 Peaking gain 0 Mac AGC control Luminance filter select: 0 = Luminance comb filter enabled (default) 1 = Luminance chroma trap filter enabled Peaking gain (sharpness): 00 = 0 (default) 01 = 0.5 10 = 1 11 = 2 Information on peaking frequency: ITU-R BT.601 sampling rate: all standards—peaking center frequency is 2.
2.20.12 Hue Control Register (does not apply to SECAM) Address 0Bh Default 00h 7 6 5 4 3 2 1 0 3 2 1 0 Hue control Hue control: 0111 1111 = +180 degrees 0000 0000 = 0 degrees (default) 1000 0000 = −180 degrees 2.20.13 Contrast Control Register Address 0Ch Default 80h 7 6 5 4 Contrast control Contrast control: 1111 1111 = 255 (maximum contrast) 1000 0000 = 128 (default) 0000 0000 = 0 (minimum contrast) 2.20.
YCbCr output format: 000 = 8-bit 4:2:2 YCbCr with discrete sync output 001 = Reserved 010 = Reserved 011 = Reserved 100 = Reserved 101 = Reserved 110 = Reserved 111 = 8-bit ITU-R BT.656 interface with embedded sync output (default) 2.20.
2.20.
2.20.18 Active Video Cropping Start Pixel LSB Register Address 12h Default 00h 7 6 5 4 3 Reserved 2 AVID active 1 0 AVID start pixel LSB [1:0] AVID active: 0 = AVID out active in VBLK (default) 1 = AVID out inactive in VBLK Active video cropping start pixel LSB [1:0]: The TVP5150A decoder updates the AVID start values only when this register is written to.
2.20.21 Genlock and RTC Register Address 15h Default 01h 7 6 5 Reserved 4 3 F/V bit control 2 1 Reserved 0 GLCO/RTC F/V bit control BIT 5 0 0 BIT 4 0 1 1 0 1 1 NUMBER OF LINES F BIT V BIT Standard ITU-R BT.656 ITU-R BT.656 Nonstandard even Force to 1 Switch at field boundary Nonstandard odd Toggles Switch at field boundary Standard ITU-R BT.656 ITU-R BT.656 Nonstandard Toggles Switch at field boundary Standard ITU-R BT.656 ITU-R BT.
2.20.22 Horizontal Sync (HSYNC) Start Register Address 16h Default 80h 7 6 5 4 3 2 1 0 HSYNC start HSYNC start: 1111 1111 = −127 x 4 pixel clocks 1111 1110 = −126 x 4 pixel clocks 1111 1101 = −125 x 4 pixel clocks 1000 0000 = 0 pixel clocks (default) 0111 1111 = 1 x 4 pixel clocks 0111 1110 = 2 x 4 pixel clocks 0000 0000 = 128 x 4 pixel clocks BT.656 EAV Code YOUT [7:0] U Y V Y F F 0 0 0 0 X Y 8 0 BT.
2.20.
2.20.25 Chrominance Control #1 Register Address 1Ah Default 0Ch 7 6 Reserved 5 4 3 2 Color PLL reset Chrominance adaptive comb filter enable (ACE) Chrominance comb filter enable (CE) 1 0 Automatic color gain control Color PLL reset: 0 = Color PLL not reset (default) 1 = Color PLL reset Color PLL phase is reset to zero and the color PLL reset bit then immediately returns to zero.
2.20.
2.20.27 Interrupt Reset Register B Address 1Ch Default 00h 7 6 5 4 3 2 1 0 Software initialization reset Macrovision detect changed reset Reserved Field rate changed reset Line alternation changed reset Color lock changed reset H/V lock changed reset TV/VCR changed reset Interrupt reset register B is used by the external processor to reset the interrupt status bits in interrupt status register B. Bits loaded with a 1 allow the corresponding interrupt status bit to reset to 0.
2.20.28 Interrupt Enable Register B Address 1Dh Default 00h 7 6 Software initialization occurred enable Macrovision detect changed 5 4 3 2 1 0 Reserved Field rate changed Line alternation changed Color lock changed H/V lock changed TV/VCR changed Interrupt enable register B is used by the external processor to mask unnecessary interrupt sources for interrupt B. Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin.
2.20.29 Interrupt Configuration Register B Address 1Eh Default 00h 7 6 5 4 3 2 1 0 Reserved Interrupt polarity B Interrupt polarity B: 0 = Interrupt B is active low (default). 1 = Interrupt B is active high. Interrupt polarity B must be same as interrupt polarity A bit at bit 0 of the interrupt configuration register A at address C2h. Interrupt configuration register B is used to configure the polarity of interrupt B on the external interrupt pin.
2.20.32 Cr Gain Factor Register Address 2Dh 7 6 5 4 3 2 1 0 Cr gain factor This is a read-only register that provides the gain applied to the Cr in the YCbCr data stream. 2.20.33 Macrovision On Counter Register Address 2Eh Default 0Fh 7 6 5 4 3 2 1 0 Macrovision on counter This register allows the user to determine how many consecutive frames in which the Macrovision AGC pulses have to be detected before the decoder decides that the Macrovision AGC pulses are present. 2.20.
2.20.37 ROM Major Version Register Address 82h Default 03h 7 6 5 4 3 2 1 0 2 1 0 1 0 ROM major version† † This register can contain a number from 0x01 to 0xFF. Value = 0x03 2.20.38 ROM Minor Version Register Address 83h Default 21h 7 6 5 4 3 ROM minor version† † This register can contain a number from 0x01 to 0xFF. Value = 0x21 2.20.39 Vertical Line Count MSB Register Address 84h 7 6 5 4 3 2 Reserved Vertical line count MSB Vertical line count bits [9:8] 2.20.
2.20.41 Interrupt Status Register B Address 86h 7 6 5 4 3 2 1 0 Software initialization Macrovision detect changed Command ready Field rate changed Line alternation changed Color lock changed H/V lock changed TV/VCR changed Software initialization: 0 = Software initialization is not ready (default). 1 = Software initialization is ready. Macrovision detect changed: 0 = Macrovision detect status has not changed (default). 1 = Macrovision detect status has changed.
2.20.43 Status Register #1 Address 88h 7 6 5 4 3 2 1 0 Peak white detect status Line-alternating status Field rate status Lost lock detect Color subcarrier lock status Vertical sync lock status Horizontal sync lock status TV/VCR status Peak white detect status: 0 = Peak white is not detected. 1 = Peak white is detected.
2.20.44 Status Register #2 Address 89h 7 6 5 4 3 2 Reserved Weak signal detection PAL switch polarity Field sequence status AGC and offset frozen status 1 0 Macrovision detection Weak signal detection: 0 = No weak signal 1 = Weak signal mode PAL switch polarity of first line of odd field: 0 = PAL switch is 0 1 = PAL switch is 1 Field sequence status: 0 = Even field 1 = Odd field AGC and offset frozen status: 0 = AGC and offset are not frozen. 1 = AGC and offset are frozen.
2.20.46 Status Register #4 Address 8Bh 7 6 5 4 3 2 1 0 Subcarrier to horizontal (SCH) phase SCH (color PLL subcarrier phase at 50% of the falling edge of horizontal sync of line one of odd field; step size 360_/256): 0000 0000 = 0.00_ 0000 0001 = 1.41_ 0000 0010 = 2.81_ 1111 1110 = 357.2_ 1111 1111 = 358.6_ 2.20.
2.20.48 Closed Caption Data Registers Address 90h−93h Address 7 6 5 4 3 2 90h Closed caption field 1 byte 1 91h Closed caption field 1 byte 2 92h Closed caption field 2 byte 1 93h Closed caption field 2 byte 2 1 0 These registers contain the closed caption data arranged in bytes per field. 2.20.
2.20.50 VPS Data Registers Address 9Ah–A6h ADDRESS 7 6 5 4 3 9Ah VPS byte 1 9Bh VPS byte 2 9Ch VPS byte 3 9Dh VPS byte 4 9Eh VPS byte 5 9Fh VPS byte 6 A0h VPS byte 7 A1h VPS byte 8 A2h VPS byte 9 A3h VPS byte 10 A4h VPS byte 11 A5h VPS byte 12 A6h VPS byte 13 2 1 0 These registers contain the entire VPS data line except the clock run-in code or the start code. 2.20.
2.20.
2.20.
2.20.55 Interrupt Status Register A Address C0h Default 00h 7 6 Lock state interrupt Lock interrupt 5 4 Reserved 3 2 1 0 FIFO threshold interrupt Line interrupt Data interrupt The interrupt status register A can be polled by the host processor to determine the source of an interrupt. After an interrupt condition is set it can be reset by writing to this register with a 1 in the appropriate bit(s). Lock state interrupt: 0 = TVP5150A is not locked to the video signal (default).
2.20.56 Interrupt Enable Register A Address C1h Default 00h 7 6 5 4 Reserved Lock interrupt enable Cycle complete interrupt enable Bus error interrupt enable 3 2 1 0 Reserved FIFO threshold interrupt enable Line interrupt enable Data interrupt enable The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin.
2.20.57 Interrupt Configuration Register A Address C2h Default 04h 7 6 5 4 3 Reserved 2 1 0 YCbCr enable (VDPOE) Interrupt A Interrupt polarity A YCbCr enable (VDPOE): 0 = YCbCr pins are high impedance. 1 = YCbCr pins are active if other conditions are met (default). Interrupt A (read-only): 0 = Interrupt A is not active on the external pin (default). 1 = Interrupt A is active on the external pin. Interrupt polarity A: 0 = Interrupt A is active low (default). 1 = Interrupt A is active high.
Table 2−13.
2.20.59 VDP Status Register Address C6h 7 6 5 4 3 2 1 0 FIFO full error FIFO empty TTX available CC field 1 available CC field 2 available WSS available VPS available VITC available The VDP status register indicates whether data is available in either the FIFO or data registers, and status information about the FIFO. Reading data from the corresponding register does not clear the status flags automatically. These flags are only reset by writing a 1 to the respective bit.
2.20.61 FIFO Interrupt Threshold Register Address C8h Default 80h 7 6 5 4 3 2 1 0 Number of words This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value (default 80h). This interrupt must be enabled at address C1h. 1 word equals 2 bytes. 2.20.62 FIFO Reset Register Address C9h Default 00h 7 6 5 4 3 2 1 0 2 1 0 Any data Writing any data to this register resets the FIFO and clears any data present. 2.20.
2.20.65 FIFO Output Control Register Address CDh Default 01h 7 6 5 4 3 2 1 0 Reserved Host access enable This register is programmed to allow I2C access to the FIFO or allowing all VDP data to go out the video port. Host access enable: 0 = Output FIFO data to the video output Y[9:2] 1 = Allow I2C access to the FIFO data (default) 2.20.66 Full Field Enable Register Address CFh Default 00h 7 6 5 4 Reserved 3 2 1 0 Full field enable This register enables the full field mode.
2.20.
These registers program the specific VBI standard at a specific line in the video field. Bit 7: 0 = Disable filtering of null bytes in closed caption modes 1 = Enable filtering of null bytes in closed caption modes (default) In teletext modes, bit 7 enables the data filter function for that particular line. If it is set to 0, then the data filter passes all data on that line. Bit 6: 0 = Send VBI data to registers only. 1 = Send VBI data to FIFO and the registers. Teletext data only goes to FIFO.
3 Electrical Specifications 3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)† Supply voltage range: IOVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.5 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.3 V PLL_AVDD to PLL_AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.3 V CH1_AVDD to CH1_AGND . .
3.3 Electrical Characteristics DVDD = 1.8 V, PLL_AVDD = 1.8 V, CH1_AVDD = 1.8 V, IOVDD = 3.3 V For minimum/maximum values: TA = 0°C to 70°C, and for typical values: TA = 25°C unless otherwise noted 3.3.1 DC Electrical Characteristics TEST CONDITIONS (see NOTE 1) PARAMETER MIN TYP MAX UNIT IDD(IO_D) IDD(D) Digital I/O supply current Color bar input 4.8 mA Digital core supply current Color bar input 25.3 mA IDD(PLL_A) IDD(CH1_A) Analog PLL supply current Color bar input 5.
3.3.3 Timing 3.3.3.1 Clocks, Video Data, Sync Timing TEST CONDITIONS (see NOTE 2) PARAMETER Duty cycle PCLK MIN TYP MAX 40% 50% 60% UNIT t1 t2 PCLK high time 18.5 ns PCLK low time 18.5 ns t3 t4 PCLK fall time 10% to 90% 4 ns PCLK rise time 90% to 10% 4 ns t5 t6 Output hold time 2 ns Output delay time 3 8 ns NOTE 2: Measured with a load of 15 pF. t1 t2 PCLK t3 Y, C, AVID, VS, HS, FID t4 VOH Valid Data Valid Data VOL t5 t6 Figure 3−1.
3.3.3.2 I2C Host Port Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 t2 Bus free time between STOP and START 1.3 µs Setup time for a (repeated) START condition 0.6 µs t3 t4 Hold time (repeated) START condition 0.6 µs Setup time for a STOP condition 0.6 ns t5 t6 Data setup time 100 t7 t8 Rise time VC1(SDA) and VC0(SCL) signal Cb Capacitive load for each bus line I2C clock frequency fI2C Data hold time ns 0 0.
4 Example Register Settings The following example register settings are provided only as a reference. These settings, given the assumed input connector, video format, and output format, set up the TVP5150A decoder and provide video output. Example register settings for other features and the VBI data processor are not provided here. 4.1 Example 1 4.1.
5 Application Information 5.1 Application Example C2 C1 1uF 1uF C3 PDN INTERQ/GPCL AVID HSYNC 1uF 0.1uF R1 0.1uF C4 CH1_IN AVDD PDN INTERQ/GPCL AVID HSYNC IO_DVDD 0.1uF R5 1 2 3 4 5 6 7 8 C5 CH2_IN 37.4 Ω AVDD R6 C6 37.4 Ω S1 1 24 23 22 21 20 19 18 17 2 R4 1.2K VSYNC/PALI FID/GLCO SDA SCL VSYNC/PALI FID/GLCO DVDD C7 0.1uF 9 10 11 12 13 14 15 16 OSC OSC_IN TVP5150A VSYNC/PALI FID/GLCO SDA SCL DVDD DGND YOUT0 YOUT1 PCLK/SCLK IO_DVDD YOUT7 YOUT6 YOUT5 YOUT4 YOUT3 YOUT2 0.
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