Datasheet

TVP5150AM1

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SLES209E–NOVEMBER 2007– REVISED OCTOBER 2011

3.21.71 Pixel Alignment Registers

Address CBh CCh

Default 4Eh 00h

Address 7 6 5 4 3 2 1 0

CBh Switch pixel [7:0]

CCh Reserved Switch pixel [9:8]

These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP

controller initiates the program from one line standard to the next line standard; for example, the previous

line of teletext to the next line of closed caption. This value must be set so that the switch occurs after the

previous transaction has cleared the delay in the VDP, but early enough to allow the new values to be

programmed before the current settings are required.

3.21.72 FIFO Output Control Register

Address CDh

Default 01h

7 6 5 4 3 2 1 0

Reserved Host access

enable

This register is programmed to allow I

C access to the FIFO or to allow all VDP data to go out the video

port as ancillary data.

Host access enable

0 = Output FIFO data to the video output Y[7:0] as ancillary data

1 = Read FIFO data via I2C register B0h (default)

3.21.73 Full Field Enable Register

Address CFh

Default 00h

7 6 5 4 3 2 1 0

Reserved Full field enable

This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines

in the line mode registers programmed with FFh are sliced with the definition of register FCh. Values other

than FFh in the line mode registers allow a different slice mode for that particular line.

Full field enable

0 = Disable full field mode (default)

1 = Enable full field mode

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