Datasheet

TVP5150AM1

SLES209E–NOVEMBER 2007–REVISED OCTOBER 2011

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3.21.38 RAM Version LSB Register

Address 33h

Default 00h

7 6 5 4 3 2 1 0

RAM version LSB [7:0]

RAM Version LSB [7:0]: This register identifies the LSB of the RAM code revision number.

3.21.39 Patch Write Address

Address 7Eh

Default 00h

7 6 5 4 3 2 1 0

R/W[7:0]

This register is used for downloading firmware patch code. Please refer to the patch load application note

for more detail. This register must not be written to or read from during normal operation.

3.21.40 Patch Code Execute

Address 7Fh

Default 00h

7 6 5 4 3 2 1 0

R/W[7:0]

Writing to this register following a firmware patch load restarts the CPU and initiates execution of the patch

code. This register must not be written to or read from during normal operation.

3.21.41 MSB of Device ID Register

Address 80h

Default 51h

7 6 5 4 3 2 1 0

MSB of device ID

This register identifies the MSB of the device ID. Value = 51h.

3.21.42 LSB of Device ID Register

Address 81h

Default 50h

7 6 5 4 3 2 1 0

LSB of device ID

This register identifies the LSB of the device ID. Value = 51h.

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