Datasheet

TVP5150AM1

SLES209E–NOVEMBER 2007–REVISED OCTOBER 2011

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3.21.7 Luminance Processing Control #1 Register

Address 07h

Default 60h

7 6 5 4 3 2 1 0

2× luminance Pedestal not Disable raw Luminance bypass Luminance signal delay with respect to chrominance signal

output enable present header enabled during

vertical blanking

2× luminance output enable

0 = Output depends on bit 4, luminance bypass enabled during vertical blanking (default).

1 = Outputs 2x luminance samples during the entire frame. This bit takes precedence over bit 4.

Pedestal not present

0 = 7.5 IRE pedestal is present on the analog video input signal.

1 = Pedestal is not present on the analog video input signal (default).

Disable raw header

0 = Insert 656 ancillary headers for raw data

1 = Disable 656 ancillary headers and instead force dummy ones (40h) (default)

Luminance bypass enabled during vertical blanking

0 = Disabled. If bit 7, 2× luminance output enable, is 0, normal luminance processing occurs and

YCbCr samples are output during the entire frame (default).

1 = Enabled. If bit 7, 2× luminance output enable, is 0, normal luminance processing occurs and

YCbCr samples are output during VACTIVE and 2× luminance samples are output during VBLK.

Luminance bypass occurs for the duration of the vertical blanking as defined by registers 18h and 19h.

Luminance signal delay with respect to chrominance signal in pixel clock increments (range –8 to +7 pixel

clocks)

1111 = –8 pixel clocks delay

1011 = –4 pixel clocks delay

1000 = –1 pixel clocks delay

0000 = 0 pixel clocks delay (default)

0011 = +3 pixel clocks delay

0111 = +7 pixel clocks delay

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