Datasheet
TVP5150AM1
SLES209E–NOVEMBER 2007–REVISED OCTOBER 2011
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Table 3-11. Register Summary (continued)
REGISTER ADDRESS DEFAULT R/W
(1)
Cr gain factor 2Dh R
Macrovision on counter 2Eh 0Fh R/W
Macrovision off counter 2Fh 01h R/W
656 revision select 30h 00h R/W
Reserved 31h–32h
RAM Version LSB 33h 00h R
Reserved 34h-7Dh
Patch Write Address 7Eh 00h R/W
(2)
Patch Code Execute 7Fh 00h R/W
(2)
Device ID MSB 80h 51h R
Device ID LSB 81h 50h R
ROM version 82h 04h R
RAM version MSB 83h 00h R
Vertical line count MSB 84h R
Vertical line count LSB 85h R
Interrupt status register B 86h R
Interrupt active register B 87h R
Status register #1 88h R
Status register #2 89h R
Status register #3 8Ah R
Status register #4 8Bh R
Status register #5 8Ch R
Reserved 8Dh
Patch Read Address 8Eh 00h R/W
(2)
Reserved 8Fh
Closed caption data 90h–93h R
WSS/CGMS-A data 94h–99h R
VPS/Gemstar 2x data 9Ah–A6h R
VITC data A7h–AFh R
VBI FIFO read data B0h R
Teletext filter and mask 1 B1h–B5h 00h R/W
Teletext filter and mask 2 B6h–BAh 00h R/W
Teletext filter control BBh 00h R/W
Reserved BCh–BFh
Interrupt status register A C0h 00h R/W
Interrupt enable register A C1h 00h R/W
Interrupt configuration register A C2h 04h R/W
VDP configuration RAM data C3h DCh R/W
VDP configuration RAM address low byte C4h 0Fh R/W
VDP configuration RAM address high byte C5h 00h R/W
VDP status C6h R
FIFO word count C7h R
FIFO interrupt threshold C8h 80h R/W
FIFO reset C9h 00h W
Line number interrupt CAh 00h R/W
Pixel alignment LSB CBh 4Eh R/W
(2) These registers are used for firmware patch code and should not be written to or read from during
normal operation.
28 Functional Description Copyright © 2007–2011, Texas Instruments Incorporated
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