Datasheet

TVP5150AM1

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SLES209E–NOVEMBER 2007– REVISED OCTOBER 2011

The second phase is the data phase. In this phase, an I

C master initiates a read operation to the

TVP5150AM1 decoder by generating a start condition followed by the TVP5150AM1 I

C slave address

(see the following illustration of a read operation), in MSB first bit order, followed by a 1 to indicate a read

cycle. After an acknowledge from the TVP5150AM1 decoder, the I

C master receives one or more bytes

of data from the TVP5150AM1 decoder. The I

C master acknowledges the transfer at the end of each

byte. After the last data byte desired has been transferred from the TVP5150AM1 decoder to the master,

the master generates a not acknowledge followed by a stop.

3.15.2.1 Read Phase 1

Step 1 0

C Start (master) S

Step 2 7 6 5 4 3 2 1 0

C slave address (master) 1 0 1 1 1 0 X 0

Step 3 9

C Acknowledge (slave) A

Step 4 7 6 5 4 3 2 1 0

C Write register address (master) Addr Addr Addr Addr Addr Addr Addr Addr

Step 5 9

C Acknowledge (slave) A

Step 6 0

C Stop (master) P

3.15.2.2 Read Phase 2

Step 7 0

C Start (master) S

Step 8 7 6 5 4 3 2 1 0

C slave address (master) 1 0 1 1 1 0 X 1

Step 9 9

C Acknowledge (slave) A

Step 10 7 6 5 4 3 2 1 0

C Read data (slave) Data Data Data Data Data Data Data Data

Step 11

(1)

C Not Acknowledge (master) A

Step 12 0

C Stop (master) P

(1) Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.

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