Datasheet

Functional Description
58
SLES099C—March 2007TVP5147PFP
2.11.53 F and V Bit Control Register
Subaddress 75h
Default 12h
7 6 5 4 3 2 1 0
2 line delay Stable HS Line limit Fast lock F and V [1:0] Phase Det. HPLL
2-line delay: Enable bypass of internal 2-line delay when in VCR mode
0 = Disabled (default)
1 = Enabled
Stable HSYNC: Enable work around code which stabilizes horizontal sync in VCR mode
0 = Disabled (default)
1 = Enabled
Line limit: Enable ±30 line limit from standard lines per frame on vertical sync PLL adjustment when vertical
lock is true.
0 = Disabled (default)
1 = Enabled
Fast lock: Enable fast lock where vertical PLL is reset and a 2 sec timer is initialized when vertical lock is lost;
during time-out the detected input VSYNC is output.
0 = Disabled
1 = Enabled (default)
F and V [1:0]
F and V Lines per frame F bit V bit
00 = (default)
Standard ITU−R BT 656 ITU−R BT 656
()
Nonstandard−even Forced to 1 Switch at field boundary
Nonstandard−odd Toggles Switch at field boundary
01 =
Standard ITU−R BT 656 ITU−R BT 656
Nonstandard Toggles Switch at field boundary
10 =
Standard ITU−R BT 656 ITU−R BT 656
Nonstandard Pulsed mode Switch at field boundary
11 = Reserved
Phase Detector: Enable integral window phase detector
0 = Disabled
1 = Enabled (default)
HPLL Enable horizontal PLL to free run
0 = Disabled (default)
1 = Enabled