Datasheet

TVP5147M1
SLES140G –JULY 2005–REVISED FEBRUARY 2012 www.ti.com
Table 2-85. Vertical Line Count Register
Subaddress 9Ah–9Bh
Read only
Subaddress 7 6 5 4 3 2 1 0
9Ah Vertical line [7:0]
9Bh Reserved Vertical line [9:8]
Vertical line [9:0]:
Represent the detected a total number of lines from the previous frame. This can be used with nonstandard video signals such as a
VCR in trick mode to synchronize downstream video circuitry.
Because this register is a double-byte register, it is necessary to capture the setting into the register to ensure that the value is not
updated between reading the lower and upper bytes. To cause this register to capture the current settings, bit 0 of the status request
register (subaddress 97h) must be set to a 1b. Once the internal processor has updated and can be read. Either byte may be read first
since no further update occurs until bit 0 of 97h is set to 1b again.
Table 2-86. AGC Decrement Delay Register
Subaddress 9Eh
Default 1Eh
7 6 5 4 3 2 1 0
AGC decrement delay [7:0]
AGC decrement delay:
Number of frames to delay gain decrements
1111 1111 = 255
⋮
0001 1110 = 30 (default)
⋮
0000 0000 = 0
72 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TVP5147M1