Datasheet
Copy
Protection
Detector
VBI Data
Processor
Output
Formatter
Composite
Processor
CVBS/Y
C/CbCr
YCbCr
Y[9:0]
Timing
Processor
AVID
FID
GLCO
XTAL1
XTAL2
RESETB
CH1 A/D
CH2 A/D
HS/CS
VS/VBLK
DATACLK
C[9:0]
Host
Interface
SCL
SDA
Slice VBI Data
2×
Decimation
PWDN
2×
Decimation
TVP5147M1
SLES140G –JULY 2005–REVISED FEBRUARY 2012
www.ti.com
2.1.5 A/D Converters
All ADCs have a resolution of 11 bits and can operate up to 30 MSPS. All A/D channels receive an
identical clock from the on-chip phase-locked loop (PLL) at a frequency between 24 MHz and 30 MHz. All
ADC reference voltages are generated internally.
2.2 Digital Video Processing
Figure 2-2 is a block diagram of the TVP5147M1 digital video decoder processing. This block receives
digitized video signals from the ADCs and performs composite processing for CVBS and S-video inputs
and YCbCr signal enhancements for CVBS and S-video inputs. It also generates horizontal and vertical
syncs and other output control signals such as genlock for CVBS and S-video inputs. Additionally, it can
provide field identification, horizontal and vertical lock, vertical blanking, and active video window
indication signals. The digital data output can be programmed to two formats: 20-bit 4:2:2 with external
syncs or 10-bit 4:2:2 with embedded/separate syncs. The circuit detects pseudosync pulses, AGC pulses,
and color striping in Macrovision-encoded copy-protected material. Information present in the VBI interval
can be retrieved and either inserted in the ITU-R BT.656 output as ancillary data or stored in internal FIFO
and/or registers for retrieval via the host port interface.
Figure 2-2. Digital Video Processing Block Diagram
2.2.1 2x Decimation Filter
All input signals are typically oversampled by a factor of 2 (27 MHz). The A/D outputs initially pass through
decimation filters that reduce the data rate to 1× the pixel rate. The decimation filter is a half-band filter.
Oversampling and decimation filtering can effectively increase the overall signal-to-noise ratio by 3 dB.
2.2.2 Composite Processor
Figure 2-3 is a block diagram of the TVP5147M1 digital composite video processing circuit. This
processing circuit receives a digitized composite or S-video signal from the ADCs and performs Y/C
separation (bypassed for S-video input), chroma demodulation for PAL/NTSC and SECAM, and YUV
signal enhancements.
18 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated
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