Datasheet

SLES084C − August 2007 TVP5146

2.11.80 Interrupt Raw Status 0 Register

Subaddress F0h

Read only

7 6 5 4 3 2 1 0

FIFO THRS TTX WSS VPS VITC CC F2 CC F1 Line

FIFO THRS: FIFO threshold passed, unmasked

0 = Not passed

1 = Passed

TTX: Teletext data available unmasked

0 = Not available

1 = Available

WSS: WSS data available unmasked

0 = Not available

1 = Available

VPS: VPS data available unmasked

0 = Not available

1 = Available

VITC: VITC data available unmasked

0 = Not available

1 = Available

CC F2: CC field 2 data available unmasked

0 = Not available

1 = Available

CC F1: CC field 1 data available unmasked

0 = Not available

1 = Available

Line: Line number interrupt unmasked

0 = Not available

1 = Available

See also the interrupt raw status 1 register at subaddress F1h (see Section 2.11.81).

The host interrupt raw status 0 and 1 registers represent the interrupt status without applying

mask bits.