Datasheet

70
SLES084C − August 2007TVP5146
2.11.78 FIFO Read Data Register
Subaddress E2h
Read only
7 6 5 4 3 2 1 0
FIFO read data [7:0]
FIFO read data [7:0]: This register is provided to access VBI FIFO data through the host port. All
forms of teletext data come directly from the FIFO, while all other forms of VBI data can be
programmed to come from registers or from the FIFO. If the host port is to be used to read data
from the FIFO, then bit 0 (host access enable) in the VDP FIFO output control register at
subaddress C0h must be set to 1 (see Section 2.11.68).
2.11.79 VBUS Address Access Register
Subaddress E8h E9h EAh
Default 00h 00h 00h
Subaddress 7 6 5 4 3 2 1 0
E8h VBUS address [7:0]
E9h VBUS address [15:8]
EAh VBUS address [23:16]
VBUS address [23:0]: VBUS is a 24-bit wide internal bus. The user must program in these
registers the 24-bit address of the internal register to be accessed via host port indirect access
mode.