Datasheet

49
SLES084C − August 2007 TVP5146
2.11.36 Output Formatter 2 Register
Subaddress 34h
Default 00h
7 6 5 4 3 2 1 0
Reserved Y[9:0] enable Reserved CLK polarity Clock enable
Y[9:0] enable: Y[9:0] and C[9:0] output enable
0 = Y[9:0] and C[9:0] high impedance (default)
1 = Y [9:0] and C[9:0] active
CLK polarity:
0 = Data clocked out on the falling edge of DATACLK (default)
1 = Data clocked out on the rising edge of DATACLK
Clock enable:
0 = DATACLK outputs are high-impedance (default).
1 = DATACLK outputs are enabled.
2.11.37 Output Formatter 3 Register
Subaddress 35h
Default FFh
7 6 5 4 3 2 1 0
FSS [1:0] AVID [1:0] GLCO [1:0] FID [1:0]
FSS [1:0]: FSS terminal function select
00 = FSS is logic 0 output.
01 = FSS is logic 1 output.
10 = FSS is fast-switch input for SCART support.
11 = FSS is logic input (default).
AVID [1:0]: AVID terminal function select
00 = AVID is logic 0 output.
01 = AVID is logic 1 output.
10 = AVID is active video indicator output.
11 = AVID is logic input (default).
GLCO [1:0]: GLCO terminal function select
00 = GLCO is logic 0 output.
01 = GLCO is logic 1 output.
10 = GCLO is genlock output.
11 = GCLO is logic input (default).
FID [1:0]: FID terminal function select
00 = FID is logic 0 output.
01 = FID is logic 1 output.
10 = FID is FID output.
11 = FID is logic input (default).