Datasheet

32
SLES084C − August 2007TVP5146
Table 2−10. Registers Summary (Continued)
REGISTER NAME I
2
C SUBADDRESS DEFAULT R/W
Reserved 26h–27h
Fast-switch control 28h CCh R/W
Reserved 29h
Fast-switch SCART delay 2Ah 00h R/W
Reserved 2Bh
SCART delay 2Ch 00h R/W
CTI delay 2Dh 00h R/W
CTI control 2Eh 00h R/W
Reserved 2Fh–30h
RTC 31h 05h R/W
Sync control 32h 00h R/W
Output formatter 1 33h 40h R/W
Output formatter 2 34h 00h R/W
Output formatter 3 35h FFh R/W
Output formatter 4 36h FFh R/W
Output formatter 5 37h FFh R/W
Output formatter 6 38h FFh R/W
Clear lost lock detect 39h 00h R/W
Status 1 3Ah R
Status 2 3Bh R
AGC gain status 3Ch–3Dh R
Reserved 3Eh
Video standard status 3Fh R
GPIO input 1 40h R
GPIO input 2 41h R
Vertical line count 42h–43h R
Reserved 44h–45h R
AFE coarse gain for CH1 46h 20h R/W
AFE coarse gain for CH2 47h 20h R/W
AFE coarse gain for CH3 48h 20h R/W
AFE coarse gain for CH4 49h 20h R/W
AFE fine gain for Pb_B 4Ah–4Bh 900h R/W
AFE fine gain for Y_G_Chroma 4Ch–4Dh 900h R/W
AFE fine gain for Pr_R 4Eh–4Fh 900h R/W
AFE fine gain for CVBS_Luma 50h–51h 900h R/W
Reserved 52h–6Fh
ROM version 70h R
Reserved 71h–73h
AGC white peak processing 74h 00h R/W
Reserved 75h–77h
NOTE: R = Read only
W = Write only
R/W = Read and write
Reserved register addresses must not be written to.