Datasheet

30
SLES084C − August 2007TVP5146
The TVP5146 requires that terminal 69 (C_1/GPIO) be held LOW. If using the 20-/16-bit mode
or using this terminal as GPIO, then this terminal must be pulled low through a 2.2-kΩ pulldown
resistor (see Figure 5−1). If unused, this terminal can be shorted to ground. (Note: If using the
20-/16-bit mode and only using the 16 MSBs, it is possible to short terminal 69 to GND, but the
current for IOVDD will increase by 2 or 3 mA.)
After reset, the user must write the following I
2
C commands to the TVP5146:
STEP I
2
C SUBADDRESS I
2
C DATA
1 0xE8 0x02
2 0xE9 0x00
3 0xEA 0x80
4 0xE0 0x01
5 0xE8 0x60
6 0xE9 0x00
7 0xEA 0xB0
8 0xE0 0x01
9 0xE0 0x00
10 0x03 0x01
11 0x03 0x00
Afterward, the user programs the device as usual.
2.9 Adjusting External Syncs
The proper sequence to program the following external syncs is:
• To set NTSC, PAL-M, NTSC 443, PAL60 (525-line modes):
− Set the video standard to NTSC (register 02h)
− Set HSYNC, VSYNC, VBLK, and AVID external syncs (registers 16h through 24h)
• To set PAL, PAL-N, SECAM (625-line modes):
− Set the video standard to PAL (register 02h)
− Set HSYNC, VSYNC, VBLK, and AVID external syncs (registers 16h through 24h)
• For autoswitch, set the video standard to autoswitch (register 02h)
2.10 Internal Control Registers
The TVP5146 decoder is initialized and controlled by a set of internal registers that define the
operating parameters of the entire decoder. Communication between the external controller and
the TVP5146 decoder is through a standard I
2
C host port interface, as described earlier.
Table 2−10 shows the summary of these registers. Detailed programming information for each
register is described in the following sections. Additional registers are accessible through an
indirect procedure involving access to an internal 24-bit address wide VBUS. Table 2−11 shows
the summary of the VBUS registers.
NOTE: Do not write to reserved registers. Reserved bits in any defined register must be written
with 0s, unless otherwise noted.