Datasheet
25
SLES084C − August 2007 TVP5146
Because SDA and SCL are kept open-drain at a logic-high output level or when the bus is not
driven, the user must connect SDA and SCL to a positive supply voltage via a pullup resistor on
the board. The slave-address select signal, terminal 37 (I
2
CA), enables the use of two TVP5146
decoders tied to the same I
2
C bus by controlling the least significant bit of the I
2
C device
address.
Table 2−4. I
2
C Host Interface Terminal Description
SIGNAL TYPE DESCRIPTION
I
2
CA I Slave address selection
SCL I Input clock line
SDA I/O Input/output data line
2.6.1 Reset and I
2
C Bus Address Selection
The TVP5146 decoder can respond to two possible chip addresses. The address selection is
made at reset by an externally supplied level on the I
2
CA terminal. The TVP5146 decoder
samples the level of terminal 37 at power up or at the trailing edge of RESETB and configures
the I
2
C bus address bit A0. The I
2
CA terminal has an internal pulldown resistor to pull the
terminal low to set a zero.
Table 2−5. I
2
C Address Selection
A6 A5 A4 A3 A2 A1 A0 (I
2
CA) R/W HEX
1 0 1 1 1 0 0 (default) 1/0 B9/B8
1 0 1 1 1 0 1
†
1/0 BB/BA
†
If terminal 37 is strapped to DVDD via a 2.2-kΩ resistor, I
2
C device address A0 is set to 1.
2.6.2 I
2
C Operation
S 1011 1000 ACK Subaddress ACK Send data ACK P
Data transfers occur using the following illustrated formats.
Read from I
2
C control registers
S 1011 1000 ACK Subaddress ACK S 1011 1001 ACK Receive data NAK P
S = I
2
C bus start condition
P = I
2
C bus stop condition
ACK = Acknowledge generated by the slave
NAK = Acknowledge generated by the master, for multiple-byte read master with ACK for each byte except
last byte
Subaddrress = Subaddress byte
Data = Data byte, if more than one byte of data is transmitted (read and write), the subaddress pointer is
automatically incremented.
I
2
C bus address = Example showing that I
2
CA is in default mode. Write (B8h), read (B9h)
2.6.3 VBUS Access
The TVP5146 decoder has additional internal registers accessible through an indirect access to
an internal 24-bit address wide VBUS. Figure 2−25 shows the VBUS registers access.