Datasheet

23
SLES084C − August 2007 TVP5146
54
72
64
64
20
38
138
174
22
53 64 19
56
CbCr[9:0]
NTSC 601
PAL 601
DATACLK = 1 Pixel Clock
NTSC Sqp
PAL Sqp
64
Mode A BC
136
142
D
Cb
DATACLK
Cr Cb Cr Cb0 Cr0 Cb1 Cr1
0
HS Start
Horizontal Blanking
HS
HS Stop
A C
B
AVID
D
NOTE: AVID rising edge occurs 2 clock cycles early.
Y[9:0] Y Y Y Y Y0 Y1 Y2 Y3Horizontal Blanking
2
AVID Stop AVID Start
NOTE: 20-bit 4:2:2 timing with 1× pixel clock reference
Figure 2−23. Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode