Datasheet

93
SLES084C − August 2007 TVP5146
5 Application Information
5.1 Application Example
NOTE: If XTAL1 is connected to clock source, input voltage high must be 1.8 V.
Terminals 69 and 71 must be connected to ground through pulldown resistors.
TVP5146PFP
VI_1_A
CH1_A18GND
CH1_A18VDD
PLL_A18GND
PLL_A18VDD
XTAL2 XTAL1
VS/VBLK
HS/CS
FID
C_0 C_1
DGND
DVDD
C_2 C_3 C_4 C_5
IOGND
IOVDD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
C_6/RED
C_7/GREEN
C_8/BLUE
C_9/FSO
DGND
DVDD
Y_0
Y_1
Y_2
Y_3
Y_4
IOGND
IOVDD
Y_5
Y_6
Y_7
Y_8
Y_9
DGND
DVDD
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
12
13
14
19
20
VI_1_B
VI_1_C
CH1_A33GND
CH1_A33VDD
CH2_A33VDD
CH2_A33GND
VI_2_A
VI_2_B
VI_2_C
CH2_A18GND
CH2_A18VDD
A18VDD_REF
A18GND_REF
CH3_A18VDD
CH3_A18GND
VI_3_A
VI_3_B
VI_3_C
CH3_A33GND
CH3_A33VDD
CH4_A33VDD CH4_A33GND VI_4A CH4_A18GND CH4_A18VDD AGND DGND SCL SDA INTREQ DVDD DGND PWDN RESETB FSS AVID GLCO/I2CA IOVDD IOGND DATACLK
40 39 38 37 36 35 34 33 32 31 30 29 22 21 28 27 26 25 24 23
A3.3VDD
GND
C_7
C_8
C_9
FID
VS/VBLK
DATACLK
GLCO/I2CA
VI_1B
VI_1C
VI_2A
VI_2B
VI_3A
VI_3B
VI_2C
VI_3C
VI_4A
AVID
FSS
RESETB
PWDN
CL1
CL2
14.31818 MHz
INTREQ
SDA
SCL
Y_0
Y_1
Y_2
Y_3
Y_4
Y_5
Y_6
Y_7
Y_8
Y_9
C_6
C_3
C_4
C_5
C_2
C_1
C_0
VI_1A
HS/CS
XTAL1
XTAL2
XTAL1
XTAL2
A1.8VDD
1
2
3
I2C Address selection
1−2 Base Addr. 0xBA
2−3 Base Addr. 0xB8
GLCO/I2CA
DVDD1.8V
IOVDD3.3V
IOVDD
2.2 kΩ (2)
75 Ω
75 Ω (3)
75 Ω (3)
75 Ω (3)
2.2 kΩ
10 kΩ
10 kΩ
0.1 µF
0.1 µF (2)
0.1 µF
0.1 µF (2)
0.1 µF
0.1 µF
0.1 µF (3)
0.1 µF
0.1 µF (2)
0.1 µF
0.1 µF
0.1 µF (3)
0.1 µF (3)
0.1 µF (3)
0.1 µF
0.1 µF
2.2 kΩ
Figure 5−1. Application Example