Datasheet

TVP5146M2
www.ti.com
SLES141H JULY 2005 REVISED FEBRUARY 2012
Table 2-84. RAM Version LSB Register
Subaddress 82h
Read only
7 6 5 4 3 2 1 0
RAM version LSB [7:0]
RAM version LSB [7:0]:
This register identifies the LSB of the RAM code revision number.
Example:
Patch Release = v08.00.06
ROM Version = 08h
RAM Version MSB = 00h
RAM Version LSB = 06h
Table 2-85. Color PLL Speed Control Register
Subaddress 83h
Default 09h
7 6 5 4 3 2 1 0
Reserved Speed [3:0]
Speed [3:0]:
Color PLL speed control
1001 = Faster (default)
1010 =
1011 = Slower
Other = Reserved
Table 2-86. Status Request Register
Subaddress 97h
Default 00h
7 6 5 4 3 2 1 0
Reserved Capture
Capture:
Setting a 1b in this register causes the internal processor to capture the current settings of the AGC status and the vertical line count
registers. Because this capture is not immediate, it is necessary to check for completion of the capture by reading the capture bit
repeatedly after setting it and waiting for it to be cleared by the internal processor. Once the capture bit is 0b, the AGC status and
vertical line counters (3Ch/3Dh and 9Ah/9Bh) have been updated and can be safely read in any order.
Table 2-87. Vertical Line Count Register
Subaddress 9Ah-9Bh
Read only
Subaddress 7 6 5 4 3 2 1 0
9Ah Vertical line [7:0]
9Bh Reserved Vertical line [9:8]
Vertical line [9:0]:
Represent the detected a total number of lines from the previous frame. This can be used with nonstandard video signals, such as a
VCR in trick mode, to synchronize downstream video circuitry.
Because this register is a double-byte register, it is necessary to capture the setting into the register to ensure that the value is not
updated between reading the lower and upper bytes. To cause this register to capture the current settings, bit 0 of the status request
register (subaddress 97h) must be set to a 1b. Once the internal processor has updated and can be read, either byte may be read first,
because no further update will occur until bit 0 of 97h is set to 1b again.
Copyright © 20052012, Texas Instruments Incorporated Functional Description 73
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