Datasheet

TVP5146M2
SLES141H –JULY 2005– REVISED FEBRUARY 2012 www.ti.com
Table 2-112. Interrupt Clear 0 Register
Subaddress F6h
Read only
7 6 5 4 3 2 1 0
FIFO THRS TTX WSS/CGMS VPS/Gemstar VITC CC F2 CC F1 Line
The host Interrupt Clear 0 and Interrupt Clear 1 (see Table 2-113) registers are used by the external processor to clear the interrupt status
bits in the host Interrupt Status 0 and Interrupt Status 1 registers. When no nonmasked interrupts remain set in the registers, the external
interrupt terminal also becomes inactive.
FIFO THRS:
FIFO threshold passed clear
0 = No effect (default)
1 = Clear FIFO_THRES bit in status register 0 bit 7
TTX:
Teletext data available clear
0 = No effect (default)
1 = Clear TTX available bit in status register 0 bit 6
WSS/CGMS:
WSS/CGMS data available clear
0 = No effect (default)
1 = Clear WSS/CGMS available bit in status register 0 bit 5
VPS/Gemstar:
VPS/Gemstar data available clear
0 = No effect (default)
1 = Clear VPS/Gemstar available bit in status register 0 bit 4
VITC:
VITC data available clear
0 = Disabled (default)
1 = Clear VITC available bit in status register 0 bit 3
CC F2:
CC field 2 data available clear
0 = Disabled (default)
1 = Clear CC field 2 available bit in status register 0 bit 2
CC F1:
CC field 1 data available clear
0 = Disabled (default)
1 = Clear CC field 1 available bit in status register 0 bit 1
LINE:
Line number interrupt clear
0 = Disabled (default)
1 = Clear Line interrupt available bit in status register 0 bit 0
86 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated
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