Datasheet

TVP5146M2

SLES141H –JULY 2005– REVISED FEBRUARY 2012

www.ti.com

Table 2-108. Interrupt Status 0 Register

Subaddress F2h

Read only

7 6 5 4 3 2 1 0

FIFO THRS TTX WSS/CGMS VPS/Gemstar VITC CC F2 CC F1 Line

Interrupt Status 0 and Interrupt Status 1 (see Table 2-109) registers represent the interrupt status after applying mask bits. Therefore, the

status bits are the result of a logical AND between the raw status and mask bits. The external interrupt terminal is derived from this register

as an OR function of all nonmasked interrupts in this register.

Reading data from the corresponding register does not clear the status flags automatically. These flags are reset using the corresponding

bits in the Interrupt Clear 0 and Interrupt Clear 1 registers.

FIFO THRS:

FIFO threshold passed, masked

0 = Not passed

1 = Passed

TTX:

Teletext data available masked

0 = Not available

1 = Available

WSS/CGMS:

WSS/CGMS data available masked

0 = Not available

1 = Available

VPS/Gemstar:

VPS/Gemstar data available masked

0 = Not available

1 = Available

VITC:

VITC data available masked

0 = Not available

1 = Available

CC F2:

CC field 2 data available masked

0 = Not available

1 = Available

CC F1:

CC field 1 data available masked

0 = Not available

1 = Available

Line:

Line number interrupt masked

0 = Not available

1 = Available

Submit Documentation Feedback

Product Folder Link(s): TVP5146M2