Datasheet

TVP5146M2
www.ti.com SLES141H –JULY 2005– REVISED FEBRUARY 2012
Table 2-77. F-Bit and V-Bit Control 2 Register
Subaddress 75h
Default 16h
7 6 5 4 3 2 1 0
Reserved Fast lock F and V [1:0] Phase detector HPLL
Fast lock:
Enable fast lock where vertical PLL is reset and a 2-second timer is initialized when vertical lock is lost; during time-out the detected
input VSYNC is output.
0 = Disabled
1 = Enabled (default)
F and V [1:0]
F AND V LINES PER FRAME F BIT V BIT
Standard ITU-R BT 656 ITU-R BT 656
00 Nonstandard even Forced to 1 Switch at field boundary
Nonstandard odd Toggles Switch at field boundary
Standard ITU-R BT 656 ITU-R BT 656
01
Nonstandard Toggles Switch at field boundary
Standard ITU-R BT 656 ITU-R BT 656
10
Nonstandard Pulsed mode Switch at field boundary
11 Reserved
Phase detector:
Enable integral window phase detector
0 = Disabled
1 = Enabled (default)
HPLL:
Enable horizontal PLL to free run
0 = Disabled (default)
1 = Enabled
Table 2-78. VCR Trick Mode Control Register
Subaddress 76h
Default 8Ah
7 6 5 4 3 2 1 0
Switch header Horizontal shake threshold [6:0]
Switch header:
When in VCR trick mode, the header noisy area around the head switch is skipped.
0 = Disabled
1 = Enabled (default)
Horizontal shake threshold [6:0]:
000 0000 = Zero threshold
000 1010 = 0Ah (default)
111 1111 = Largest threshold
Table 2-79. Horizontal Shake Increment Register
Subaddress 77h
Default 64h
7 6 5 4 3 2 1 0
Horizontal shake increment [7:0]
Horizontal shake increment [7:0]:
000 0000 = 0 000
1010 = 64h (default)
111 1111 = FFh
Copyright © 2005–2012, Texas Instruments Incorporated Functional Description 71
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