Datasheet

TVP5146M2
SLES141H –JULY 2005– REVISED FEBRUARY 2012 www.ti.com
Table 2-50. Output Formatter Control 2 Register
Subaddress 34h
Default 00h
7 6 5 4 3 2 1 0
Reserved Y [9:0] enable Reserved CLK polarity Clock enable
Y [9:0] enable:
Y_[9:0] and C_[9:0] output enable
0 = Y_[9:0] and C_[9:0] high-impedance (default)
1 = Y_[9:0] and C_[9:0] active
CLK polarity:
0 = Data clocked out on the falling edge of DATACLK (default)
1 = Data clocked out on the rising edge of DATACLK
Clock enable:
0 = DATACLK outputs are high-impedance (default)
1 = DATACLK outputs are enabled
Table 2-51. Output Formatter Control 3 Register
Subaddress 35h
Default FFh
7 6 5 4 3 2 1 0
FSS [1:0] AVID [1:0] GLCO [1:0] FID [1:0]
FSS [1:0]:
FSS terminal function select
00 = FSS is logic 0 output
01 = FSS is logic 1 output
10 = Reserved
11 = FSS is logic input (default)
AVID [1:0]:
AVID terminal function select
00 = AVID is logic 0 output
01 = AVID is logic 1 output
10 = AVID is active video indicator output
11 = AVID is logic input (default)
GLCO [1:0]:
GLCO terminal function select
00 = GLCO is logic 0 output
01 = GLCO is logic 1 output
10 = GLCO is genlock output
11 = GLCO is logic input (default)
FID [1:0]:
FID terminal function select
00 = FID is logic 0 output
01 = FID is logic 1 output
10 = FID is FID output
11 = FID is logic input (default)
56 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated
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