Datasheet

TVP5146M2
SLES141H –JULY 2005– REVISED FEBRUARY 2012 www.ti.com
Table 2-10. I
2
C Register Summary
(1)
(continued)
I
2
C
REGISTER NAME DEFAULT R/W
SUBADDRESS
AGC increment delay 79h 1Eh R/W
Reserved 7Ah-7Fh
Chip ID MSB 80h R
Chip ID LSB 81h R
RAM Version LSB 82h R
CPLL speed control 83h 09h R/W
Reserved 84h-96h
Status request 97h 00h R/W
Reserved 98h-99h
Vertical line count 9Ah-9Bh R
Reserved 9Ch-9Dh
AGC decrement delay 9Eh 00h R/W
Reserved 9Fh-B0h
VDP TTX filter 1 mask 1 B1h 00h R/W
VDP TTX filter 1 mask 2 B2h 00h R/W
VDP TTX filter 1 mask 3 B3h 00h R/W
VDP TTX filter 1 mask 4 B4h 00h R/W
VDP TTX filter 1 mask 5 B5h 00h R/W
VDP TTX filter 2 mask 1 B6h 00h R/W
VDP TTX filter 2 mask 2 B7h 00h R/W
VDP TTX filter 2 mask 3 B8h 00h R/W
VDP TTX filter 2 mask 4 B9h 00h R/W
VDP TTX filter 2 mask 5 BAh 00h R/W
VDP TTX filter control BBh 00h R/W
VDP FIFO word count BCh R
VDP FIFO interrupt threshold BDh 80h R/W
Reserved BEh
VDP FIFO reset BFh 00h R/W
VDP FIFO output control C0h 00h R/W
VDP line number interrupt C1h 00h R/W
VDP pixel alignment C2h-C3h 01Eh R/W
Reserved C4h-D5h
VDP line start D6h 06h R/W
VDP line stop D7h 1Bh R/W
VDP global line mode D8h FFh R/W
VDP full field enable D9h 00h R/W
VDP full field mode DAh FFh R/W
Reserved DBh-DFh
VBUS data access with no VBUS address increment E0h 00h R/W
VBUS data access with VBUS address increment E1h 00h R/W
FIFO read data E2h R
Reserved E3h-E7h
VBUS address access E8h-EAh 00 0000h R/W
Reserved EBh-EFh
Interrupt raw status 0 F0h
Interrupt raw status 1 F1h
Interrupt status 0 F2h R/W
40 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TVP5146M2