Datasheet

TVP5146M2

SLES141H –JULY 2005– REVISED FEBRUARY 2012

www.ti.com

List of Figures

1-1 Functional Block Diagram....................................................................................................... 13

1-2 Terminal Assignments Diagram ................................................................................................ 13

2-1 Analog Processors and A/D Converters ...................................................................................... 16

2-2 Digital Video Processing Block Diagram ...................................................................................... 18

2-3 Composite and S-Video Processor ............................................................................................ 19

2-8 Luminance Edge-Enhancer Peaking Block Diagram ........................................................................ 22

2-9 Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling ............................................................ 22

2-10 Y Component Gain, Offset, Limit............................................................................................... 23

2-11 CbCr Component Gain, Offset, Limit .......................................................................................... 23

2-12 Reference Clock Configurations................................................................................................ 24

2-13 RTC Timing ....................................................................................................................... 24

2-14 Vertical Synchronization Signals for 525-Line System ...................................................................... 28

2-15 Vertical Synchronization Signals for 625-Line System ...................................................................... 29

2-16 Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode.................................................................. 30

2-17 Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode.................................................................. 31

2-18 VSYNC Position With Respect to HSYNC.................................................................................... 31

2-19 VBUS Access ..................................................................................................................... 34

2-20 Reset Timing...................................................................................................................... 37

2-21 Teletext Filter Function .......................................................................................................... 76

3-1 Clocks, Video Data, and Sync Timing ......................................................................................... 95

3-2 I

C Host Port Timing ............................................................................................................. 95

5-1 Example Application Circuit ................................................................................................... 100