Datasheet

22
53 64 19
56
CbCr[9:0]
NTSC 601
PAL 601
DATACLK = 1 Pixel Clock
64
Mode A B C
136
142
D
Cb
DATACLK
Cr Cb Cr Cb0 Cr0 Cb1 Cr1
0
HS Start
Horizontal Blanking
HS
HS Stop
A C
B
AVID
D
NOTE: AVID rising edge occurs 2 clock cycles early.
Y[9:0]
Y Y Y Y Y0 Y1 Y2 Y3Horizontal Blanking
2
AVID Stop AVID Start
TVP5146M2
SLES141H –JULY 2005– REVISED FEBRUARY 2012 www.ti.com
NOTE: 20-bit 4:2:2 timing with 1× pixel clock reference
Figure 2-17. Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode
30 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated
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