Datasheet

NTSC 601 106
PAL 601 112
128
128
42
48
276
288
Y[9:0]
DATACLK = 2 Pixel Clock
Mode A B C D
Cb
DATACLK
EAV
1
Y Cr Y
EAV
2
EAV
3
EAV
4
SAV
1
SAV
2
SAV
3
SAV
4
Cb0 Y0 Cr0 Y1
0
HS Start
Horizontal Blanking
HS
HS Stop
A C
B
AVID
D
AVID Stop AVID Start
TVP5146M2
www.ti.com SLES141H –JULY 2005– REVISED FEBRUARY 2012
NOTE: ITU-R BT.656 10-bit 4:2:2 timing with 2× pixel clock reference
Figure 2-16. Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode
Copyright © 2005–2012, Texas Instruments Incorporated Functional Description 29
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