Datasheet

Composite and S-V ideo Processor
Y/C
Separation
5-line
Adaptive
Comb
Luma
Processing
Chroma
Processing
ADC1
ADC2
ADC3
ADC4
M
U
X
Component
Processor
CVBS/Y
C
Y/G
Pb/B
Pr/R
Gain/Offset
Color
Space
Conversion
C
Y
Output
Formatter
Y[9:0]
YCbCr
VBI
Data
Slicer
Copy
Protection
Detector
C[9:0]
Host
Interface
Timing Processor
With Sync Detector
VI_1_A
VI_1_B
VI_1_C
VI_2_A
VI_2_B
VI_2_C
VI_3_A
VI_3_B
VI_3_C
VI_4_A
CVBS/
Y/G
CVBS/
Pb/B/C
CVBS/
Pr/R/C
CVBS/Y
CVBS/Y/G
Analog Front End
Sampling
Clock
GPIO
FSS
HS/CS
VS/VBLK
FID
AVID
XTAL1 XTAL2
DATACLK
RESETB
GLCO
PWDN
SCL
SDA
YCbCr
TVP5146M2
SLES141H –JULY 2005– REVISED FEBRUARY 2012 www.ti.com
1.7 Functional Block Diagram
Figure 1-1. Functional Block Diagram
12 Introduction Copyright © 2005–2012, Texas Instruments Incorporated
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