Datasheet
XI
VSSOSC
XO
CL1
CL2
Crystal
TUSB9261
www.ti.com
SLLSE67F –MARCH 2011–REVISED JULY 2013
6 CLOCK CONNECTIONS
6.1 Clock Source Requirements
The TUSB9261 supports an external oscillator source or a crystal unit. If a clock is provided to XI instead
of a crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a
crystal is used, the connection needs to follow the guidelines below.
Since XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short
as possible and away from any switching leads. It is also recommended to minimize the capacitance be-
tween XI and XO. This can be accomplished by connecting the VSSOSC lead to the two external capaci-
tors CL1 and CL2 and shielding them with the clean ground lines. The VSSOSC should not be connected
to PCB ground when using a crystal.
Load capacitance (C
load
) of the crystal varying with the crystal vendors is the total capacitance value of the
entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and CL2
in Figure 6-1. The trace length between the decoupling capacitors and the corresponding power pins on
the TUSB9261 needs to be minimized. It is also recommended that the trace length from the capacitor
pad to the power or ground plane be minimized.
Figure 6-1. Typical Crystal Connections
6.2 Clock Source Selection Guide
Reference clock jitter is an important parameter. Jitter on the reference clock will degrade both the trans-
mit eye and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing system
performance. Additionally, a particularly jittery reference clock may interfere with PLL lock detection
mechanism, forcing the Lock Detector to issue an Unlock signal. A good quality, low jitter reference clock
is required to achieve compliance with supported USB3.0 standards. For example, USB3.0 specification
requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random phase jitter calculated
after applying jitter transfer function - JTF). As the PLL typically has a number of additional jitter
components, the Reference Clock jitter must be considerably below the overall jitter budget.
Copyright © 2011–2013, Texas Instruments Incorporated CLOCK CONNECTIONS 17
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