Datasheet

TUSB9261
www.ti.com SLLSE67F –MARCH 2011–REVISED JULY 2013
Table 5-6. JTAG, GPIO, and PWM Signals
TERMINAL
I/O DESCRIPTION
PIN
NAME
NO.
I
JTAG_TCK 25 JTAG test clock
PD
I
JTAG_TDI 26 JTAG test data in
PU
O
JTAG_TDO 27 JTAG test data out
PD
I
JTAG_TMS 28 JTAG test mode select
PU
I
JTAG_TRSTz 29 JTAG test reset
PD
I/O GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a
GPIO9/UART_TX 6
PU UART channel. This pin defaults to a general purpose output.
I/O GPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART
GPIO8/UART_RX 5
PU channel. This pin defaults to a general purpose output.
I/O
GPIO7 16
PD
I/O
GPIO6 15
PD
I/O
GPIO5 14
PD
I/O
GPIO4 13
PD
Configurable as general purpose input/outputs
I/O
GPIO3 11
PD
I/O
GPIO2 10
PD
I/O
GPIO1 9
PD
I/O
GPIO0 8
PD
O
PWM0 2
PD
(1)
Pulse Width Modulation (PWM). Can be used to drive status LED's.
O
PWM1 3
PD
(1)
(1) PWM pull down resistors are disabled by default. A firmware modification is required to turn them on. All other internal pull up/down
resistors are enabled by default.
Copyright © 2011–2013, Texas Instruments Incorporated SIGNAL DESCRIPTIONS 15
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