Datasheet

TUSB9261

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SLLSE67F –MARCH 2011–REVISED JULY 2013

4.4 Power Up and Reset Sequence

The TUSB9261 does not have specific power sequencing requirements with respect to the core power

(VDD), I/O power (VDD33), or analog power (VDDA33). The core power (VDD) or IO power (VDD33) may

be powered up for an indefinite period of time while others are not powered up if all of these constraints

are met:

• All maximum ratings and recommended operating conditions are observed.

• All warnings about exposure to maximum rated and recommended conditions are observed, par-

ticularly junction temperature. These apply to power transitions as well as normal operation.

• Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of

the device.

• Bus contention while VDD33 is powered down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. It is powered

down when it is below that range, either stable or in transition.

A minimum reset duration of 2 ms is required. This is defined as the time when the power supplies are in

the recommended operating range to the de-assertion of GRSTz.

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