Datasheet

ROM
RAM
ARM
Cortex M3
Power
and
Reset
Distribution
JTAG
Clock
Generation
TCK
TMS
TDO
TDI
TRST
XI
XO
SCI
(UART)
Watchdog
SPI
Timer
GPIO
PWM
U
a
r
tR
X
U
a
r
TX
S
C
L
K
Timer
Data Path
RAM
80 kB
SA
T
A
TX+
SA
T
A
TX-
SA
T
ARX+
SA
T
ARX-
SATA II
PHY
USB SS
PHY
USB HS/FS
PHY
SATA
AHCI
USB 3.0
Device
Controller
SSTX+ SSTX-
SSRX+ SSRX-
VBUS
VDD3.3
VDD1.8
VDD1.1
DATA_OUT
DATA_IN
CS[2:0]
GPIO[11:0]
PWM[1:0]
DP/DM
USB_R1
USB_R1RTN
GRSTz
TUSB9260
www.ti.com SLLS962D– DECEMBER 2009–REVISED MAY 2011
Figure 2-1. Device Block Diagram
Copyright © 2009–2011, Texas Instruments Incorporated INTRODUCTION 7
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