Datasheet

Not Recommended for New Designs

TUSB8040

SLLSE42I –SEPTEMBER 2010–REVISED SEPTEMBER 2013

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Table 2-5. Test and Miscellaneous Signals (continued)

SIGNAL NAME TYPE PIN NO. DESCRIPTION

Full power management enable/SMBus address bit 1.

The value of the terminal is sampled at the de-assertion of reset to set the power switch

control follows:

0 = Full power management supported

FULLPWRMGMTz_S

1 = Full Power management not supported

I, PU 41

MBA1

Full power management is the ability to control power to the downstream ports of the

TUSB8040 using the PWRON0z_BATEN0 terminal. When SMBus mode is enabled using

SMBUSz, this terminal sets the value of the SMBus slave address bit 1. SMBus slave

address bits 2 and 3 are always 1 for the TUSB8040.

Can be left unconnected if full power management and SMBus are not implemented.

2.6 Power Signals

Table 2-6. Power Signals

SIGNAL NAME TYPE PIN NO. DESCRIPTION

4, 19, 21,

38, 43, 58

VDD33 P 3.3-V power rail

68, 72, 77,

1, 5, 10,

11, 16, 20,

26, 32, 37,

VDD11 P 1.1-V power rail

42, 46, 51,

52, 57, 61,

67, 71

GND G 64, 81 Ground, Power Pad

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