Datasheet
TUSB8040A
www.ti.com
SLLSEA7F –MAY 2012–REVISED SEPTEMBER 2013
6.3 Thermal Information
TUSB8040A
THERMAL METRIC RKM UNITS
100 PINS
θ
JA
Junction-to-ambient thermal resistance
(1)
25.6
θ
JCtop
Junction-to-case (top) thermal resistance
(2)
9.5
θ
JB
Junction-to-board thermal resistance
(3)
15.2
°C/W
ψ
JT
Junction-to-top characterization parameter
(4)
0.1
ψ
JB
Junction-to-board characterization parameter
(5)
7.5
θ
JCbot
Junction-to-case (bottom) thermal resistance
(6)
0.4
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
6.4 3.3-V I/O Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER OPERATION TEST CONDITIONS MIN MAX UNIT
V
IH
High-level input voltage
(1)
VDD33 2 VDD33 V
0 0.8
V
IL
Low-level input voltage
(1)
VDD33 V
JTAG pins only 0 0.55
V
I
Input voltage 0 VDD33 V
V
O
Output voltage
(2)
0 VDD33 V
t
t
Input transition time (t
rise
and t
fall
) 0 25 ns
V
hys
Input hysteresis
(3)
0.13 x VDD33 V
V
OH
High-level output voltage VDD33 I
OH
= -4 mA 2.4 V
V
OL
Low-level output voltage VDD33 I
OL
= 4 mA 0.4 V
I
OZ
High-impedance, output current
(2)
VDD33 V
I
= 0 to VDD33 ±20 µA
High-impedance, output current with
I
OZP
internal pullup or pulldown VDD33 V
I
= 0 to VDD33 ±225 µA
resistor
(4)
I
I
Input current
(5)
VDD33 V
I
= 0 to VDD33 ±15 µA
(1) Applies to external inputs and bidirectional buffers.
(2) Applies to external outputs and bidirectional buffers.
(3) Applies to GRSTz.
(4) Applies to pins with internal pullups/pulldowns.
(5) Applies to external input buffers.
Copyright © 2012–2013, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 29
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