Datasheet

TUSB8040A
www.ti.com
SLLSEA7F MAY 2012REVISED SEPTEMBER 2013
3.4.18 Device Status and Command Register
Table 3-36. Register Offset F8h
Bit No. 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0
Table 3-37. Bit Descriptions Device Status and Command Register
Bit Field Name Access Description
7:2 RSVD RO Reserved. Read only, returns 0 when read.
SMBus interface reset. This bit resets the SMBus slave interface to its
default state and loads the registers back to their GRSTz values. This bit
1 smbusRst RSU
is set by writing a 1 and is cleared by hardware on completion of the
reset. A write of 0 has no effect. (Not used with I
2
C)
Configuration active. This bit indicates that configuration of the
TUSB8040A is currently active. The bit is set by hardware when the
device enters the I
2
C or SMBus mode. The TUSB8040A does not
connect on the upstream port while this bit is 1.When in I
2
C mode, the bit
0 cfgActive RCU
is cleared by hardware when the TUSB8040A exits the I
2
C mode. When
in the SMBus mode, this bit must be cleared by the SMBus host in order
to exit the configuration mode and allow the upstream port to connect.
The bit is cleared by a writing 1. A write of 0 has no effect.
Copyright © 2012–2013, Texas Instruments Incorporated FUNCTIONAL DESCRIPTION 25
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