Datasheet

TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011 www.ti.com
7 MSI-X MEMORY MAPPED REGISTER SPACE
7.1 The MSI-X Table and PBA in Memory Mapped Register Space
The TUSB73X0 includes the MSI-X Table and PBA in memory mapped register space. These registers
are accessible via the address programmed into the Base Address Register 2/3.
Table 7-1. MSI-X Table and PBA Register Map
Register Name Offset
Entry 0 Message Address 0000h
Entry 0 Message Upper Address 0004h
Entry 0 Message Data 0008h
Entry 0 Vector Control 000Ch
Entry 1 Message Address 0010h
Entry 1 Message Upper Address 0014h
Entry 1 Message Data 0018h
Entry 1 Vector Control 001Ch
Entry 2 Message Address 0020h
Entry 2 Message Upper Address 0024h
Entry 2 Message Data 0028h
Entry 2 Vector Control 002Ch
Entry 3 Message Address 0030h
Entry 3 Message Upper Address 0034h
Entry 3 Message Data 0038h
Entry 3 Vector Control 003Ch
Entry 4 Message Address 0040h
Entry 4 Message Upper Address 0044h
Entry 4 Message Data 0048h
Entry 4 Vector Control 004Ch
Entry 5 Message Address 0050h
Entry 5 Message Upper Address 0054h
Entry 5 Message Data 0058h
Entry 5 Vector Control 005Ch
Entry 6 Message Address 0060h
Entry 6 Message Upper Address 0064h
Entry 6 Message Data 0068h
Entry 6 Vector Control 006Ch
Entry 7 Message Address 0070h
Entry 7 Message Upper Address 0074h
Entry 7 Message Data 0078h
Entry 7 Vector Control 007Ch
Reserved 0080h-0FFFh
Pending Bits 7 through 0 1000h
Reserved 1001h-1FFFh
Refer to the PCI Local Bus Specification, Revision 3.0 for descriptions of these registers.
98 MSI-X MEMORY MAPPED REGISTER SPACE Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TUSB7320 TUSB7340