Datasheet
TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011
www.ti.com
Table 6-32. Port Status and Control Register Description (continued)
26 WDE * rw Wake on Disconnect Enable.
25 WCE * rw Wake on Connect Enable.
24 RSVD r Reserved. Return zero when read.
Port Config Error Change. This field is only valid for USB 3.0 protocol
23 CEC * rc or r
ports. For USB 2.0 protocol ports, this bit is reserved.
22 PLC * rc Port Link State Change.
21 PRC * rc Port Reset Change.
20 OCC * rc Over-current Change.
Warm Port Reset Change. This field is only valid for USB 3.0 protocol
19 WRC * rc or r
ports. For USB 2.0 protocol ports, this bit is reserved.
18 PEC * rc Port Enabled/Disabled Change.
17 CSC * rc Connect Status Change.
16 LWS w Port Link State Write Strobe. This bit returns a zero when read.
Port Indicator Control. Since the TUSB73X0 does not support port
15:14 PIC * rw
indicators, this field has no effect.
13:10 PORT_SPEED * r Port Speed
9 PP * rw Port Power.
8:5 PLS * rw Port Link State
4 PR * rs Port Reset.
3 OCA r Over-current Active.
2 RSVD r Reserved. Returns zero when read.
1 PED * rc Port Enabled/Disabled.
0 CCS * r Current Connect Status.
6.3.10 Port PM Status and Control Register (USB 3.0 Ports)
The TUSB73X0 implements a Port PM Status and Control Register for each port that is implemented. The
number of Port PM Status and Control Registers is the same as the value in the MAX_PORTS field in the
Host Controller Structural Parameters 1 Register (see Section 6.2.3).
Operational Base register offset:404h + (10h*(n-1))), where n = Port Number
Register type:Read-Only, Read/Write
Default value: 0000 0000h
Table 6-33. HC Operational Register (Operational Base + 404h + (10h*(n-1))), where n = Port Number
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Table 6-34. Port PM Status and Control Register (USB 3.0) Description
Bit Field Name Access Description
31:17 RSVD r Reserved. Returns zeros when read.
16 FLA rw Force Link PM Accept.
15:8 U2_TIMEOUT* rw U2 Timeout.
7:0 U1_TIMEOUT* rw U1 Timeout.
86 xHCI MEMORY MAPPED REGISTER SPACE Copyright © 2011, Texas Instruments Incorporated
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