Datasheet

TUSB7320, TUSB7340

SLLSE76E–MARCH 2011– REVISED JULY 2011

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5.9 Advanced Error Capabilities and control Register

The Advanced Error Capabilities and Control Register allows the system to monitor and control the

advanced error reporting capabilities.

PCI Express Extended Register Offset: 118h

Default value: 0000 0050h

Table 5-14. PCI Express Extended Register 118h

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

No.

Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

State

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

No.

Reset

0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

State

Table 5-15. Bit Descriptions – Advanced Error Capabilities and Control Register

(1)

Bit Field Name Access Description

31:9 RSVD r Reserved. Returns zeros when read.

Extended CRC Check Enable.

8† ECRC_CHK_EN † rw 0 – Extended CRC checking is Disabled

1 – Extended CRC checking is Enabled

Extended CRC Check Capable. This read-only bit returns a value of ‘1’

7 ECRC_CHK_CAPABLE r indicating that the TUSB73X0 is capable of checking extended CRC

information.

Extended CRC Generation Enable.

6† ECRC_GEN_EN † rw 0 – Extended CRC generation is Disabled

1 – Extended CRC generation is Enabled

Extended CRC Generation Capable. This read-only bit returns a value of

5 ECRC_GEN_CAPABLE r ‘1’ indicating that the TUSB73X0 is capable of generating extended CRC

information.

First Error Pointer. This five bit value reflects the bit position within the

4:0† FIRST_ERR † ru Uncorrectable Error Status Register corresponding to the class of the

first error condition that was detected.

(1) Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset

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Product Folder Link(s): TUSB7320 TUSB7340