Datasheet
TUSB7320, TUSB7340
www.ti.com
SLLSE76E–MARCH 2011– REVISED JULY 2011
5.3 Next Capability Offset / Capability Version Register
This read-only register identifies the next location in the PCI Express Extended Capabilities link list. The
upper 12 bits in this register shall be 150h, indicating that the Device Serial Number Capability starts at
offset 150h. The least significant four bits identify the revision of the current capability block as 2h.
PCI Express Extended Register Offset: 100h
Register type:Read-Only
Default value: 1502h
Table 5-3. PCI Express Extended Register 102h
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0
State
5.4 Uncorrectable Error Status Register
The Uncorrectable Error Status Register reports the status of individual errors as they occur. Software
may clear these bits only by writing a 1 to the desired location.
PCI Express Extended Register Offset: 104h
Register type:Read-Only, Read/Clear
Default value: 0000 0000h
Table 5-4. PCI Express Extended Register 104h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Table 5-5. Custom PHY Transmit/Receive Control Register Description
(1)
Bit Field Name Access Description
31:21 RSVD r Reserved. Returns zeros when read.
Unsupported Request Error. This bit is asserted when an Unsupported
20† UR_ERROR † rcu
Request is received.
Extended CRC Error. This bit is asserted when an Extended CRC error
19† ECRC_ERROR † rcu
is detected.
18† MAL_TLP † rcu Malformed TLP. This bit is asserted when a malformed TLP is detected.
Receiver Overflow. This bit is asserted when the flow control logic
17† RX_OVERFLOW † rcu detects that the transmitting device has illegally exceeded the number of
credits that were issued.
Unexpected Completion. This bit is asserted when a completion packet is
16† UNXP_CPL † rcu
received that does not correspond to an issued request.
Completer Abort. This bit is asserted when the TUSB73X0 signals a
15† CPL_ABORT † rcu
Completer Abort.
Completion Timeout. This bit is asserted when no completion has been
14† CPL_TIMEOUT † rcu
received for an issued request before the timeout period.
(1) Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset
Copyright © 2011, Texas Instruments Incorporated PCI EXPRESS EXTENDED CONFIGURATION SPACE 67
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Product Folder Link(s): TUSB7320 TUSB7340