Datasheet
TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011
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Table 4-100. USB Control Register Description
(1)(2)
(continued)
Bit Field Name Access Description
USB Port 3 Disable. When this bit is set to ‘1’, port 3 of the TUSB73X0 is
10† PORT3_DIS† rw disabled. For the TUSB7320 Port 3 is not present and this bit has no
effect.
USB Port 2 Disable. When this bit is set to ‘1’, port 2 of the TUSB73X0 is
9† PORT2_DIS† rw
disabled.
USB Port 1 Disable. When this bit is set to ‘1’, port 1 of the TUSB73X0 is
8† PORT1_DIS† rw
disabled.
USB 3.0 Port 4 Non-Removable. When this bit is set to ‘1’, the
TUSB73X0 forces the DR bit to ‘1’ in the Port Status and Control
7† USB3_PORT4_NON_REM† rw
Register corresponding to USB 3.0 Port 4. For the TUSB7320 Port 4 is
not present and this bit has no effect.
USB 3.0 Port 3 Non-Removable. When this bit is set to ‘1’, the
TUSB73X0 forces the DR bit to ‘1’ in the Port Status and Control
6† USB3_PORT3_NON_REM† rw
Register corresponding to USB 3.0 Port 3. For the TUSB7320 Port 3 is
not present and this bit has no effect.
USB 3.0 Port 2 Non-Removable. When this bit is set to ‘1’, the
5† USB3_PORT2_NON_REM† rw TUSB73X0 forces the DR bit to ‘1’ in the Port Status and Control
Register corresponding to USB 3.0 Port 2.
USB 3.0 Port 1 Non-Removable. When this bit is set to ‘1’, the
4† USB3_PORT1_NON_REM† rw TUSB73X0 forces the DR bit to ‘1’ in the Port Status and Control
Register corresponding to USB 3.0 Port 1.
USB 2.0 Port 4 Non-Removable. When this bit is set to ‘1’, the
TUSB73X0 forces the DR bit to ‘1’ in the Port Status and Control
3† USB2_PORT4_NON_REM† rw
Register corresponding to USB 2.0 Port 4. For the TUSB7320 Port 4 is
not present and this bit has no effect.
USB 2.0 Port 3 Non-Removable. When this bit is set to ‘1’, the
TUSB73X0 forces the DR bit to ‘1’ in the Port Status and Control
2† USB2_PORT3_NON_REM† rw
Register corresponding to USB 2.0 Port 3. For the TUSB7320 Port 3 is
not present and this bit has no effect.
USB 2.0 Port 2 Non-Removable. When this bit is set to ‘1’, the
1† USB2_PORT2_NON_REM† rw TUSB73X0 forces the DR bit to ‘1’ in the Port Status and Control
Register corresponding to USB 2.0 Port 2.
USB 2.0 Port 1 Non-Removable. When this bit is set to ‘1’, the
0† USB2_PORT1_NON_REM† rw TUSB73X0 forces the DR bit to ‘1’ in the Port Status and Control
Register corresponding to USB 2.0 Port 1.
4.65 De-Emphasis and Swing Control Register
This register is used to control the de-emphasis and transmit swing settings for each of the USB 3.0 ports
when the default setting is overridden through the Custom PHY Transmit/Receive Control Register. This
register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset.
PCI register offset: E4h
Register type:Read/Write
Default value: 0000 0000h
Table 4-101. PCI Register E4h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
62 CLASSIC PCI CONFIGURATION SPACE Copyright © 2011, Texas Instruments Incorporated
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