Datasheet

TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011 www.ti.com
4.60 Subsystem Access Register
This register is a read/write register and the contents of this register are aliased to the Subsystem Vendor
ID and Subsystem ID Registers at PCI Offsets 2Ch and 2Eh. This register is reset by a PCI Express reset
(PERST#), a GRST#, or the internally-generated power-on reset.
PCI register offset: D0h
Register type:Read/Write
Default value: 0000 0000h
Table 4-91. PCI Register D0h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Table 4-92. Subsystem Access Register Description
Bit Field Name Access Description
Subsystem ID. The value written to this field is aliased to the Subsystem
31:16† SubsystemID† rw
ID Register at PCI Offset 2Eh.
Subsystem Vendor ID. The value written to this field is aliased to the
15:0† SubsystemVendorID† rw
Subsystem Vendor ID Register at PCI Offset 2Ch.
4.61 General Control 0 Register
This register is a read/write register is used to control various functions of the TUSB73X0. This register is
reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset.
PCI register offset: D4h
Register type:Read/Write
Default value: 0000 0D9Bh
Table 4-93. PCI Register D4h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1
State
58 CLASSIC PCI CONFIGURATION SPACE Copyright © 2011, Texas Instruments Incorporated
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