Datasheet
TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011
www.ti.com
Table 4-70. Link Control 2 Register Description
Bit Field Name Access Description
15:13 RSVD r Reserved. Returns zeros when read.
Compliance De-Emphasis. This bit is sticky and is only reset by a Global
12 COMPLIANCE_DEEMPH* rw
Reset.
11 COMPLIANCE_SOS* rw Compliance SOS. This bit is sticky and is only reset by a Global Reset.
Enter Modified Compliance. This bit is sticky and is only reset by a
10 ENT_MOD_COMPLIANCE* rw
Global Reset.
9:7 TRANSMIT_MARGIN* rw Transmit Margin. This bit is sticky and is only reset by a Global Reset.
6 SEL_DEEMPH r Selectable De-Emphasis. This bit has no function and is read only zero.
Hardware Autonomous Speed Disable. This bit is read only zero since
5 HW_AUTO_SPEED_DIS r
this function is not supported.
4 ENTER_COMPL* rw Enter Compliance. This bit is sticky and is only reset by a Global Reset.
3:0 TGT_LINK_SPEED* rw Target Link Speed. This bit is sticky and is only reset by a Global Reset.
4.48 Link Status 2 Register
The Link Status 2 Register indicates current state of the PCI Express Link.
PCI register offset: A2h
Register type:Read-only
Default value: 000xh
Table 4-71. PCI Register A2h
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x
State
Table 4-72. Link Status 2 Register Description
Bit Field Name Access Description
15:1 RSVD r Reserved. Returns zeros when read.
0 DEEMPH_LEVEL r Current De-Emphasis Level.
4.49 Serial Bus Data Register
The Serial Bus Data register is used to read and write data on the serial bus interface. When writing data
to the serial bus, this register must be written before writing to the Serial Bus Address register to initiate
the cycle. When reading data from the serial bus, this register will contain the data read after the
REQBUSY (bit 5 Serial Bus Control Register) bit is cleared. This register is reset by a PCI Express reset
(PERST#), a GRST#, or the internally-generated power-on reset.
PCI register offset: B0h
Register type:Read/Write
Default value: 00h
Table 4-73. PCI Register B0h
Bit No. 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0
52 CLASSIC PCI CONFIGURATION SPACE Copyright © 2011, Texas Instruments Incorporated
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