Datasheet

TUSB7320, TUSB7340

www.ti.com

SLLSE76E–MARCH 2011– REVISED JULY 2011

4.27 Power Management Data Register

This read-only register is not applicable to the TUSB73X0 and returns 00h when read.

PCI register offset: 47h

Default value: 00h

Table 4-36. PCI Register 47h

Bit No. 7 6 5 4 3 2 1 0

Reset State 0 0 0 0 0 0 0 0

4.28 MSI Capability ID Register

This read-only register identifies the linked list item as the register for Message Signaled Interrupts

Capabilities. The register returns 05h when read.

PCI register offset: 48h

Default value: 05h

Table 4-37. PCI Register 48h

Bit No. 7 6 5 4 3 2 1 0

Reset State 0 0 0 0 0 1 0 1

4.29 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the

TUSB73X0. This register reads 70h pointing to the PCI Express Capability registers.

PCI register offset: 49h

Default value: 70h

Table 4-38. PCI Register 49h

Bit No. 7 6 5 4 3 2 1 0

Reset State 0 1 1 1 0 0 0 0

4.30 MSI Message Control Register

The register is used to control the sending of MSI messages.

PCI register offset: 4Ah

Default value: 0086h

Table 4-39. PCI Register 4Ah

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

No.

Reset

0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0

State

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Product Folder Link(s): TUSB7320 TUSB7340