Datasheet

TUSB7320, TUSB7340

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SLLSE76E–MARCH 2011– REVISED JULY 2011

4.22 Capability ID Register

This read-only register identifies the linked list item as the register for PCI Power management. The

PCI register offset: 40h

Default value: 01h

Table 4-29. PCI Register 40h

Bit No. 7 6 5 4 3 2 1 0

Reset State 0 0 0 0 0 0 0 1

4.23 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the

TUSB73X0. This register reads 48h pointing to the MSI Capability registers.

PCI register offset: 41h

Default value: 48h

Table 4-30. PCI Register 41h

Bit No. 7 6 5 4 3 2 1 0

Reset State 0 1 0 0 1 0 0 0

4.24 Power Management Capabilities Register

The read-only register indicates the capabilities of the TUSB73X0 related to PCI power management.

PCI register offset: 42h

Default value: xxx3h

Table 4-31. PCI Register 42h

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

No.

Reset

x 1 1 1 1 1 1 x x x 0 0 0 0 1 1

State

Table 4-32. Power Management Capabilities Register Description

Bit Field Name Access Description

PME# support. This five-bit field indicates the power states from which

15:11 PME_SUPPORT r the TUSB73X0 may assert PME#. If the AUX_DET pin is ‘1’, this field is

‘11111’. If the AUX_DET pin is ‘0’, this field is ‘01111’.

This bit returns a 1 when read, indicating that the function supports the

10 D2_SUPPORT r

D2 device power state.

This bit returns a 1 when read, indicating that the function supports the

9 D1_SUPPORT r

D1 device power state.

3.3 Vaux auxiliary current requirements. If the AUX_DET pin is ‘1’, this

8:6 AUX_CURRENT r

field is 010. IF the AUX_DET pin is ‘0’, this field is ‘000’.

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Product Folder Link(s): TUSB7320 TUSB7340