Datasheet
TUSB7320, TUSB7340
www.ti.com
SLLSE76E–MARCH 2011– REVISED JULY 2011
4 CLASSIC PCI CONFIGURATION SPACE
4.1 The PCI Configuration Map
The programming model of the TUSB73X0 USB 3.0 Host Controller is compliant to the standard PCI
device programming model. The PCI configuration map uses the type 0 PCI header.
All bits marked with a '*' are sticky bits and are reset by a global reset (GRST) or the internally-generated
power-on reset. All bits marked with a '†' are reset by a PCI Express reset (PERST), a GRST, or the
internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset,
PERST, GRST, or the internally-generated power-on reset.
Table 4-1. PCI Configuration Register Map
REGISTER NAME OFFSET
Device ID Vendor ID 000h
Status Command 004h
Class Code Revision ID 008h
BIST Header Type Latency Timer Cache Line Size 00Ch
Base Address Register 0 010h
Base Address Register 1 014h
Base Address Register 2 018h
Base Address Register 3 01Ch
Reserved 020h-028h
Subsystem ID Subsystem Vendor ID 02Ch
Reserved 030h
Reserved Capabilities Pointer 034h
Reserved 038h
Max Latency Min Grant Interrupt Pin Interrupt Line 03Ch
Power Management Capabilities Next Item Pointer PM CAP ID 040h
PM Data (RSVD) PMCSR_BSE Power Management CSR 044h
MSI Message Control Next Item Pointer MSI CAP ID 048h
MSI Message Address 04Ch
MSI Upper Message Address 050h
Reserved MSI Message Data 054h
Reserved 058h-05Ch
Reserved FLADJ SBRN 60h
Reserved 064h-06Ch
PCI Express Capabilities Register Next Item Pointer PCI Express Capability ID 070h
Device Capabilities 074h
Device Status Device Control 078h
Link Capabilities 07Ch
Link Status Link Control 080h
Reserved 084h-090h
Device Capabilities2 094h
Device Status2 Device Control2 098h
Link Capabilities2 09Ch
Link Status2 Link Control2 0A0h
Reserved 0A4h-0ACh
Serial Bus CSR Serial Bus Slave Address Serial Bus Index Serial Bus Data 0B0h
GPIO Data GPIO Control 0B4h
Reserved 0B8h-0BCh
Copyright © 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE 29
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