Datasheet

VDD11

VDDA_3P3

and VDD33

PCIE_REFCLK

PERST#

TUSB7320, TUSB7340

www.ti.com

SLLSE76E–MARCH 2011– REVISED JULY 2011

3.1.2 Power-Down Sequence

1. Assert PERST# to the device.

2. Remove the reference clock.

3. Remove the 3.3-V and 1.1-V voltages

See the power power-down sequencing diagram in Figure 3-2. If the VDD33_AUX terminal is to remain

powered after a system shutdown, then the host controller power-down sequence is exactly the same as

shown in Figure 3-2.

Figure 3-2. Power-Down Sequence

3.2 Two-Wire Serial-Bus Interface

The host controller provides a two-wire serial-bus interface to load subsystem identification information

and specific register defaults from an external EEPROM. The serial-bus interface signals include SDA and

SCL. The use of an external EEPROM is optional. The TUSB73x0 will function with the default settings.

For motherboard down applications, BIOS can be used to set all of the options available on the

TUSB73x0.

On a PCIe Add-in Card, an EEPROM is only needed if a any of the following is true:

• Use of a crystal other than 48 MHz.

• Mark one or more USB ports as non-removable.

• Disable one or more USB ports.

• Set a PCIe Subsystem ID and Subsystem Vendor ID.

• Change the default de-emphasis/swing/equalizer settings of the SuperSpeed USB ports.

• Change the default L0s and L1 latency values for PCIe.

• Change the default PWRON polarity to active high instead of active low.

3.2.1 Serial-Bus Interface Implementation

To enable the serial-bus interface, a pull-up resistor must be implemented on the SCL signal. At the rising

edge of PERST# or GRST#, whichever occurs later in time, the SCL terminal is checked for a pull-up

resistor. If one is detected, then bit 3 (SBDETECT) in the serial-bus control and status register (see

Section 4.52) is set. Software may disable the serial-bus interface at any time by writing a 0b to the

SBDETECT bit. If no external EEPROM is required, then the serial-bus interface is permanently disabled

by attaching a pulldown resistor to the SCL signal.

The host controller implements a two-terminal serial interface with one clock signal (SCL) and one data

signal (SDA). The SCL signal is a unidirectional output from the host controller and the SDA signal is

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Product Folder Link(s): TUSB7320 TUSB7340