Datasheet

TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011 www.ti.com
Contents
1 INTRODUCTION ................................................................................................................. 13
1.1 Features .................................................................................................................... 13
1.2 Target Applications ........................................................................................................ 13
2 OVERVIEW ....................................................................................................................... 14
2.1 Description ................................................................................................................. 14
2.2 Related Documents ....................................................................................................... 15
2.3 Document's Conventions ................................................................................................. 15
2.4 Available Options .......................................................................................................... 15
2.5 ORDERING INFORMATION ............................................................................................. 15
2.6 Terminal Assignments .................................................................................................... 16
2.7 Terminal Descriptions ..................................................................................................... 18
3 FEATURE/PROTOCOL DESCRIPTIONS ................................................................................ 22
3.1 Power-Up/-Down Sequencing ........................................................................................... 22
3.1.1 Power-Up Sequence ........................................................................................... 22
3.1.2 Power-Down Sequence ........................................................................................ 23
3.2 Two-Wire Serial-Bus Interface ........................................................................................... 23
3.2.1 Serial-Bus Interface Implementation ......................................................................... 23
3.2.2 Serial-Bus Interface Protocol .................................................................................. 25
3.2.3 Serial-Bus EEPROM Application ............................................................................. 27
3.3 System Management Interrupt ........................................................................................... 28
4 CLASSIC PCI CONFIGURATION SPACE ............................................................................... 29
4.1 The PCI Configuration Map .............................................................................................. 29
4.2 Vendor ID Register ........................................................................................................ 30
4.3 Device ID Register ........................................................................................................ 30
4.4 Command Register ........................................................................................................ 31
4.5 Status Register ............................................................................................................ 32
4.6 Class Code and Revision ID Register .................................................................................. 33
4.7 Cache Line Size Register ................................................................................................ 33
4.8 Latency Timer Register ................................................................................................... 34
4.9 Header Type Register .................................................................................................... 34
4.10 BIST Register .............................................................................................................. 34
4.11 Base Address Register 0 ................................................................................................. 35
4.12 Base Address Register 1 ................................................................................................. 35
4.13 Base Address Register 2 ................................................................................................. 36
4.14 Base Address Register 3 ................................................................................................. 36
4.15 Subsystem Vendor ID Register .......................................................................................... 37
4.16 Subsystem ID Register ................................................................................................... 37
4.17 Capabilities Pointer Register ............................................................................................. 37
4.18 Interrupt Line Register .................................................................................................... 38
4.19 Interrupt Pin Register ..................................................................................................... 38
4.20 Min Grant Register ........................................................................................................ 38
4.21 Max Latency Register ..................................................................................................... 38
4.22 Capability ID Register ..................................................................................................... 39
4.23 Next Item Pointer Register ............................................................................................... 39
4.24 Power Management Capabilities Register ............................................................................. 39
2 Contents Copyright © 2011, Texas Instruments Incorporated